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Notice: The information in this document is subject to change without notice

3/3.3/4.0 V µP Supervisor Circuits

ASM706 P/ R/ S/ T/ J

ASM708 R/ S/ T/ J

October 2003

rev 1.0

Detailed Descriptions

A

proper

reset

input

enables

a

microprocessor/

microcontroller to start in a known state. ASM706 P/ R/ S/ T/

J and ASM708 R/ S/ T/ J assert reset to prevent code

execution errors during power-up, power-down and brown-

out conditions.

RESET/RESET Operation

The RESET/RESET signals are designed to start or return a

µP/µC to a known state.

be asserted. During a power-up sequence, the reset outputs

remain asserted until the supply rises above the threshold

level. The resets are deasserted approximately 200ms after

crossing the threshold.

level, the reset outputs are asserted. If a brownout occurs

during an already initiated reset period, the reset period will

extend for an additional reset period of 200ms.

The ASM708 devices have dual reset outputs, one active

LOW and one active HIGH. The ASM706P has a single

active HIGH reset and the ASM706/R/S/T/J devices have an

active LOW reset output.

Manual Reset (MR)

The active-LOW manual reset input is pulled high by an

internal 20k

Ω pull-up resistor and can be driven low by

CMOS/TTL logic or a mechanical switch to ground. An

external debounce circuit is

unnecessary since the 140ms minimum reset time will

debounce mechanical pushbutton switches. The minimum

MR input pulse width is 0.5

floating.

By connecting the watchdog output (WDO) and MR, a

watchdog timeout forces a RESET to be generated.

Watchdog Timer

A watchdog timer available on the ASM706P/R/S/T/J

monitors

µP/µC activity. An output line on the processor is

used to toggle the WDI line. If the line is not toggled within 1.6

seconds on the Watchdog Input (WDI), the internal timer puts

the Watchdog Output (WDO) into a LOW state. WDO will

remain LOW until a toggle is detected at WDI.

The watchdog function is disabled, meaning it is cleared and

not counting, if WDI is floated or connected to a three-stated

circuit. The watchdog timer is also disabled if RESET is

asserted. When RESET becomes inactive and the WDI input

Alliance

Part #

RESET

Polarity

Threshold

Watchdog

Timer

ASM706P

HIGH

2.63V

YES

ASM706R

LOW

2.63V

YES

ASM706S

LOW

2.93V

YES

ASM706T

LOW

3.08V

YES

ASM706J

LOW

4.00V

YES

ASM708R

HIGH & LOW

2.63V

NO

ASM708S

HIGH & LOW

2.93V

NO

ASM708T

HIGH & LOW

3.08V

NO

ASM708J

HIGH & LOW

4.00V

NO

Figure 1: WDI Three-state operation