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ASM1810 Datasheet(PDF) 3 Page - Alliance Semiconductor Corporation |
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ASM1810 Datasheet(HTML) 3 Page - Alliance Semiconductor Corporation |
3 / 9 page 3 of 9 Notice: The information in this document is subject to change without notice Low Power, 5V µP Reset ASM1810 February 2005 rev 1.4 Application Information Operation - Power Monitor The ASM1810 detects out-of-tolerance power supply conditions. It resets a processor during power-up, power-down and issues a reset to the system processor when the monitored power supply voltage is below the reset threshold. When an out-of-tolerance VCC voltage is detected, the RESET signal is asserted. On power-up, RESET is kept active (LOW) for approximately 150ms after the power supply voltage has reached the selected tolerance. This allows the power supply and microprocessor to stabilize before RESET is released. Output Conditions The ASM1810 active LOW reset signal is valid as long as VCC remains above 1.2V. However the RESET output on the ASM1810 uses a push-pull drive stage that can maintain a valid output below 1.2V. To sink current with VCC below 1.2V, a resistor can be connected from the reset pin (RESET) to Ground (see Figure 1). This configuration will give a valid value on the RESET output with VCC approaching 0V. During both power up and down, this configuration will draw current when the RESET is in the high state. A value of 100k Ω should be adequate to maintain a valid connection. Microprocessor RESET RESET ASM1810 100kΩ Figure 1: RESET Valid to 0V VCC VOH RESET tRPU VCCTP (MIN) VCCTP VCCTP (MAX) tR VCC Figure 2: Timing Diagram: Power-Up VCCTP (MIN) VCCTP VCCTP (MAX) tF VCC tRPD VOL RESET Figure 3: Timing Diagram: Power-Down |
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