6.42

IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM

4 Meg (256K x 16-Bit)

Commercial and Industrial Temperature Ranges

7

NOTES:

1. A write occurs during the overlap of a LOW

CS, LOW BHE or BLE, and a LOW WE.

2. During this period, I/O pins are in the output state, and input signals must not be applied.

3. If the

CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

Timing Waveform of Write Cycle No. 3

ADDRESS

CS

3624 drw 09

(2)

WE

BHE, BLE

ADDRESS

CS

3624 drw 10

(2)

WE

BHE, BLE