10 / 35 page  April 20, 2005 Document No. 38-12025 Rev. *G 10 CY8C21x34 Final Data Sheet 1. Pin Information 1.1.3 28-Pin Part Pinout Table 1-3. 28-Pin Part Pinout (SSOP) Pin No. Type Name Description CY8C21534 28-Pin PSoC Device Digital Analog 1 IO I, M P0[7] Analog column mux input. 2 IO I, M P0[5] Analog column mux input and column output. 3 IO I, M P0[3] Analog column mux input and column output, integrating input. 4 IO I, M P0[1] Analog column mux input, integrating input. 5 IO M P2[7] 6 IO M P2[5] 7 IO I, M P2[3] Direct switched capacitor block input. 8 IO I, M P2[1] Direct switched capacitor block input. 9 Power Vss Ground connection. 10 IO M P1[7] I2C Serial Clock (SCL). 11 IO M P1[5] I2C Serial Data (SDA). 12 IO M P1[3] 13 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK. 14 Power Vss Ground connection. 15 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA. 16 IO M P1[2] 17 IO M P1[4] Optional External Clock Input (EXT- CLK). 18 IO M P1[6] 19 Input XRES Active high external reset with internal pull down. 20 IO I, M P2[0] Direct switched capacitor block input. 21 IO I, M P2[2] Direct switched capacitor block input. 22 IO M P2[4] 23 IO M P2[6] 24 IO I, M P0[0] Analog column mux input. 25 IO I, M P0[2] Analog column mux input. 26 IO I, M P0[4] Analog column mux input 27 IO I, M P0[6] Analog column mux input. 28 Power Vdd Supply voltage. LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input. A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] M,P2[7] M,P2[5] M, P2[3] M, P2[1] Vss M,I2C SCL, P1[7] M,I2C SDA, P1[5] M,P1[3] M,I2C SCL, P1[1] Vss Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P2[6],M P2[4],M P2[2],M P2[0],M XRES P1[6],M P1[4],EXTCLK,M P1[2],M P1[0],I2C SDA, M SSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 |
|
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
