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IDT70T653MS10BCI Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT70T653MS10BCI Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 24 page IDT70T653M Preliminary High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges 4 Pin Names NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on I/OX. 2. OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 3. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundry scan not be operated during sleep mode. Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables (Input) R/WL R/WR Read/Write Enable (Input) OEL OER Output Enable (Input) A0L - A18L A0R - A18R Address (Input) I/O0L - I/O35L I/O0R - I/O35R Data Input/Output SEML SEMR Semaphore Enable (Input) INTL INTR Interrupt Flag (Output) BUSYL BUSYR Busy Input BE0L - BE3L BE0R - BE3R Byte Enables (9-bit bytes) (Input) VDDQL VDDQR Power (I/O Bus) (3.3V or 2.5V)(1) (Input) OPTL OPTR Option for selecting VDDQX(1,2) (Input) ZZL ZZR Sleep Mode Pin(3) (Input) VDD Power (2.5V)(1) (Input) VSS Ground (0V) (Input) TDI Test Data Input TDO Test Data Output TCK Test Logic Clock (10MHz) (Input) TMS Test Mode Select (Input) TRST Reset (Initialize TAP Controller) (Input) 5679 tbl 01 |
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