Page 8

Version 1.4 July 2002

MR16R1622(4/8/G)AF0

MR18R1622(4/8/G)AF0(1)

AC Electrical Specifications

Adjusted

∆T

Table 8: AC Electrical Specifications

Symbol

Parameter and Conditions

Min

Typ

Max

Unit

Module Impedance of RSL Signals

25.2

28

30.8

Ω

Module Impedance of SCK and CMOS signals

23.8

28

32.2

Ω

Propagation Delay variation of RSL signals. Average clock

delay from finger to finger of all RSL clock nets (CTM,

CTMN, CFM, and CFMN)

-See

ns

∆T

PD

b,c

for 2, 4 and 8 device modules

-21

21

ps

b,c

for 16 device modules

-24

24

ps

∆T

PD-CMOS

Propagation delay variation of SCK signals with respect to an

average clock delay

-250

250

ps

∆T

PD-SCK,CMD

Propagation delay variation of CMD signals with respect to SCK

signal

-200

200

ps

Attenuation Limit

See

%

Forward crosstalk coefficient (300ps input rise time @ 20%-80%)

See

%

Backward crosstalk coefficient (300ps input rise time @ 20%-

80%)

See

%

a. Table 10 lists parameters and specifications for different storage capacity RIMM Modules that use 256Mb or 288Mb RDRAM devices.

c. If the RIMM module meets the following specification, then it is compliant to the specification. If the RIMM module does not meet these specifica

tions, then the specification can be adjusted by the “Adjusted

∆T

Table 9: Adjusted

∆T

Symbol

Parameter and Conditions

Adjusted Min/Max

Absolute

Min / Max

Unit

∆T

PD

Propagation delay variation of RSL signals with respect to

+/-[20+(18*N*

-30

30

ps

Propagation delay variation of RSL signals with respect to

+/-[24+(18*N*

-50

50

ps

a. Where:

N = Number of RDRAM devices installed on the RIMM module

∆Z0 = delta Z0% = (max Z0 - min Z0)/(min Z0)

(max Z0 and min Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the modules)