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Revision 1.2
- 9 -
24 October 2000
MTU8B54E/55E/56E/57E
MYSON
TECHNOLOGY
3.4 RESET
This device may be reset by one of the following ways:
(1) Power-on Reset : At power-up, this device will be kept in a RESET condition for a period of 18ms after
the voltage on MCLR/Vpp pin has reached a logic high level.
(2) MCLR reset (normal operation).
(3) WDT reset (normal operation).
(4) MCLR wake-up (from sleep mode).
(5) WDT wake-up (from sleep mode) : Executing the SLEEP instruction can force this device entering into
sleep mode (power saving mode). While in sleep mode, the WDT is cleared but keeps running. This
device can be awakened by WDT time-out or reset input on MCLR pin.
The contents of registers after reset are listed below:
Note: x = unknown, u = unchanged, - = unimplemented, read as “0”,
# = refer to the following table
Address
Register
Power-On Reset
/MCLR or WDT Reset
00h
INAR
xxxx xxxx
uuuu uuuu
01h
Timer0
xxxx xxxx
uuuu uuuu
02h
PC
1111 1111
1111 1111
03h
STATUS
0001 1xxx
000# #uuu
04h
FSR
1xxx xxxx
1uuu uuuu
05h
PORTA
---- xxxx
---- uuuu
06h
PORTB
xxxx xxxx
uuuu uuuu
07h
PORTC
xxxx xxxx
uuuu uuuu
07h-1Fh
General Purpose Register
xxxx xxxx
uuuu uuuu
N/A
Acc
xxxx xxxx
uuuu uuuu
N/A
IOST
1111 1111
1111 1111
N/A
T0MODE
--11 1111
--11 1111
Condition
Status:bit 4
Status:bit 3
/MCLR Reset (not during SLEEP)
u
u
/MCLR Reset during SLEEP
1
0
WDT Reset (not during SLEEP)
0
1
WDT Reset during SLEEP
0
0
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