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Revision 1.2
- 8 -
24 October 2000
MTU8B54E/55E/56E/57E
MYSON
TECHNOLOGY
3.3 I/O PORTS EQUIVALENT CIRCUIT
Note:
b : Bit position
WDT : Watchdog Timer
R : Register address
i : Immediate data
Acc : Accumulator
T0MODE : T0MODE register
PD : Power down flag
TO : Time overflow bit
IOST : I/O port status register
Z : Zero flag
C : Carry flag
DC : Digital carry flag
I : (i7i6i5i4i3i2i1i0)
R : (r6r5r4r3r2r1r0)
:Destination
If d is “0”, the result is stored in the Acc register.
If d is “1”, the result is stored back in register R.
Mnemonic
Operands
Description
Cycles
Instruction
Code
Status
Affected
DECR R, d
Decrement R
1
01 0110 drrr rrrr
Z
DECRSZ R, d
Decrement R, Skip if 0
1 or
2(skip)
01 0111 drrr rrrr
None
SUBAR R, d
Subtract Acc from R
1
01 1010 drrr rrrr
C, DC, Z
XORAR R, d
Exclusive OR Acc with R
1
01 1011 drrr rrrr
Z
ANDAR R, d
AND Acc with R
1
01 0100 drrr rrrr
Z
ADDAR R, d
Add Acc and R
1
01 0101 drrr rrrr
C, DC, Z
IORAR R, d
Inclusive OR Acc with R
1
01 1111 drrr rrrr
Z
d
0 1
,
[
]
∈
IOST
Latch
D
CK
QB
Q
Data
Latch
D
CK
QB
Q
Acc Data
IOST R
Data Bus
WR Port
RD Port
I/O Pin
Note : 1. The IOST registers are “write-only” and set upon RESET.
2. If the IOST latch is “0”, the corresponding I/O pin is in output mode;
if the IOST latch is “1”, the corresponding I/O pin is in input mode.
VDD
VSS
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