CY7C1352B
PRELIMINARY
8
Switching Characteristics Over the Operating Range[11, 12, 13]
-166
-150
-143
-133
-100
-80
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC
Clock Cycle Time
5.0
6.6
7.0
7.5
10
12.5
ns
tCH
Clock HIGH
1.4
2.5
2.8
3.0
4.0
4.0
ns
tCL
Clock LOW
1.4
2.5
2.8
3.0
4.0
4.0
ns
tAS
Address Set-Up Before CLK
Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
tCO
Data Output Valid After CLK
Rise
3.5
3.8
4.0
4.2
5.0
7.0
ns
tDOH
Data Output Hold After CLK
Rise
1.5
1.5
1.5
1.5
1.5
1.5
ns
tCENS
CEN Set-Up Before CLK Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
tCENH
CEN Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
tWES
GW, BWS[1:0] Set-Up Before
CLK Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
tWEH
GW, BWS[1:0] Hold After CLK
Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
tALS
ADV/LD Set-Up Before CLK
Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
tALH
ADV/LD Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
tDS
Data Input Set-Up Before
CLK Rise
1.5
1.5
1.7
1.7
2.0
2.5
ns
tDH
Data Input Hold After CLK
Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
tCES
Chip Enable Set-Up Before
CLK Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
tCEH
Chip Enable Hold After CLK
Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
tCHZ
Clock to High-Z[10, 12, 13, 14]
1.5
3.2
1.5
3.2
1.5
3.5
1.5
3.5
1.5
3.5
1.5
5.0
ns
tCLZ
Clock to Low-Z[10, 12, 13, 14]
1.5
1.5
1.5
1.5
1.5
1.5
ns
tEOHZ
OE HIGH to Output High-Z[10,
12, 13, 14]
3.0
3.0
4.0
4.2
5.0
7.0
ns
tEOLZ
OE LOW to Output Low-Z[10,
12, 13, 14]
0
0
0
0
0
0
ns
tEOV
OE LOW to Output Valid[12]
3.2
3.5
4.0
4.2
5.0
7.0
ns
Shaded areas contain advance information.
Notes:
12. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with A/C test conditions shown in part (a) of AC Test Loads and waveforms. Transition is measured ± 200 mV
from steady-state voltage.
13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
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