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MX86251 Datasheet(PDF) 6 Page - Macronix International |
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MX86251 Datasheet(HTML) 6 Page - Macronix International |
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6 / 32 page  6 MX86251 P/N:PM0476 REV. 1.2 , FEB 11, 1998 pare function block in the Graphics Co-processor checks each pixel against the Key color. If a match is found, the pixel is not written, preserving the background around the sprite. Thus, an irregular shape is BLTed using a fast rectangle draw. In the MX86251, the Color Key can be in the Source or the Destination bitmap.Transparent Blt uses Source Color Key. The Destination Color Key can be used to protect screen areas. A mask register is defined to allow the key color be a range of color values instead of a single value. 2.3 Memory Controller The MX86251 Memory Controller module interfaces to the frame buffer DRAM chips which can operate in either fast page mode, or Extended Data Out (EDO) mode. The frame buffer size can be 1, 2, or 4 Megabytes. Industry standard 256K by 4, by 8, or by 16 DRAM chips are sup- ported. The Memory Controller performs the page mode cycle in either 2 clock cycle or 1 clock cycle, depending on the DRAM types being used. The highest bandwidth is delivered using -50 EDO DRAM with 20 ns page cycle time and a 50 MHz memory clock, yielding a 400MB peak bandwidth. The MX86251 is capable of even higher Memory clock speed. As faster EDO DRAM (-35 with 15ns page mode cycle time) enters volume production, the MX86251 will deliver 533 MB/sec bandwidth which is comparable to premium priced DRAMs such as 66 Mhz SGRAM / SDRAM, or RAMBUS RDRAM. The center of the Memory Controller is an intricate arbi- ter which receives memory access requests from the Graphics Co-processor for Bitblt cycles, the Display con- troller for screen fetch, the Video Processor for video play- back, the PCI Bus interface for CPU access, the Hard- ware Cursor for cursor bitmap fetch, and the DRAM re- fresh cycle request.The arbiter allocates memory cycles according to priority. For example, the Display Processor has higher priority than the Graphics Co-processor. A 32-level 64-bit FIFO is implemented to buffer the pixels fetched from display memory for the screen refresh and video playback. The FIFO entries can be flexibly allocated between three different processors: Graphics, Video line 1 and Video line 2. This flexibility works to optimize per- formance across various screen resolutions and video playback operations. The Memory Controller generates all DRAM cycles. Its logic is carefully designed to optimize DRAM cycle tim- ing parameters. For example, the DRAM entry cycle which is the time from RAS precharge to the end of first CAS cycle is optimized to the minimum of 4 clock cycles, ver- sus the commonly seen 5 or 6 clock cycles in other GUI chips. Another example is that of EDO DRAM read cycle. The MX86251 eliminates the one extra clock cycle at the end of page mode cycles. Unified Memory Architecture The MX86251 fully supports the VESA Unified Memory Architecture (VUMA) standard. The Memory Controller implements the VUMA standard RQ/GNT state machine which supports two request priorities. Bus parking is pro- vided to minimize bus switch overhead. DRAM read and write operations in UMA mode can have programmable number of wait states to accommodate the wide varia- tion in main system DRAM module access speed. In ad- dition, the DRAM interface drivers have programmable drive strength to work with wide range of DRAM inter- face loading on system motherboards. 2.4 PCI Bus Interface Unit The MX86251 Bus Interface Unit (BIU) implements a glueless connection to industry standard PCI local bus which is compliant with Windows 95 Plug’n’Play require- ment. PCI bus speed can be up to 33 MHz. For peak transfer rate between host CPU and the MX86251, zero wait state PCI burst cycles are supported. The resultant 133 MB per second bandwidth greatly enhances the performance level of Graphics intensive software such as Windows GUI and AutoCAD that do lots of direct accesses to video memory. The BIU has an 8 level command and data FIFOs to buffer host transfers and enables concurrent operations of the host CPU, the graphics engine and the Video Processor. The PCI Rev. 2.1 disconnect and retry protocol is fully supported eliminating the delays of host CPU polling for BIU FIFO status. 2.5 Video Processor The MX86251 Video Processor accelerates the playback of AVI or MPEG video decoded by a software Codec such as Cinepak, Indeo, or MPEG-1. Profiling of the task load INDEX |
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