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T436416C-6S Datasheet(PDF) 7 Page - Taiwan Memory Technology |
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T436416C-6S Datasheet(HTML) 7 Page - Taiwan Memory Technology |
7 / 28 page TE CH tm T436416C TM Technology Inc. reserves the right P. 7 Publication Date: AUG. 2004 to change products or specifications without notice. Revision: A OPERATING AC PARAMETER (AC opterating conditions unless otherwise noted) Speed Version Parameter Symbol -6 -7 Unit Note Row active to row active delay tRRD(min) 12 14 ns 1 RAS to CAS delay tRCD(min) 18 20 ns 1 Row precharge time tRP(min) 18 20 ns 1 tRAS(min) 40 42 ns 1 Row active time tRAS(max) 100K ns Row cycle time (operating) tRC(min) 58 63 ns 1 Row cycle time (auto refresh) tRFC(min) 60 70 ns 1,5 Last data in to new col. Address delay tCDL(min) 1 CLK 2 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. Address to col. Address delay tCCD(min) 1 CLK 3 CAS latency=3 2 Number of valid output data CAS latency=2 1 ea 4 Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. A new command may be given tRFC after self refresh exit. |
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