K4N51163QC-ZC33 datasheet(9/64 Pages) SAMSUNG

Part #	K4N51163QC-ZC33

Description	512Mbit gDDR2 SDRAM

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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9 / 64 page

- 9 -

Rev 1.5 Oct. 2005

512M gDDR2 SDRAM

K4N51163QC-ZC

Notes:

1. Absolute Specifications (0°C

≤ TCASE ≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)

2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for

values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV;

VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.

3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.

4. Slew rate measured from VIL(AC) to VIH(AC).

5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaran-

teed by design and characterization.

6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty.

Output slew rate load :

7. DRAM output slew rate specification applies to 533Mb/sec/pin, 667Mb/sec/pin, 800Mb/sec/pin, 900Mbps/sec/pin and

1000Mbps/sec/pin speed bins.

8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS

specification.

25 ohms

VTT

Output

(VOUT)

Reference

Point

Description

Parameter

Min

Nom

Max

Unit

Note

Output impedance

Normal 18ohms

See full strength default driver characteristics

ohms

1,2

Output impedance step size for

OCD calibration

0

1.5

ohms

6

Pull-up and pull-down mismatch

0

4

ohms

1,2,3

Output slew rate

Sout

1.5

5

V/ns

1,4,5,6,7,8

(Recommended operating conditions unless otherwise noted, 0

°C ≤ Tc ≤85°C )

Note :

1. Measured with outputs open and ODT off

Parameter

Symbol

Test Condition

Version

Unit

-25

-2A

-33

-36

Operating Current

(One Bank Active)

ICC1

Burst Length=4 tRC

≥ tRC(min). IOL=0mA, tCC= tCC(min).

DQ,DM,DQS inputs changing twice per clock cycle. Address

and control inputs changing once per clock cycle

TBD

140

TBD

130

mA

Precharge Standby Current

in Power-down mode

ICC2P

CKE

≤ VIL(max), tCC= tCC(min)

TBD

10

mA

Precharge Standby Current

in Non Power-down mode

ICC2N

CKE

≥ VIH(min), CS ≥ VIH(min),tCC= tCC(min)

Address and control inputs changing once per clock cycle

TBD

40

TBD

35

mA

Active Standby Current

power-down mode

ICC3P

CKE

≤ VIL(max), tCC=

tCC(min)

Fast PDN Exit MRS(12) =

0mA

TBD

30

TBD

25

mA

Slow PDN Exit MRS(12) =

1mA

TBD

12

TBD

12

Active Standby Current in

in Non Power-down mode

ICC3N

CKE

≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) DQ,DM,DQS

inputs changing twice per clock cycle. Address and control

inputs changing once per clock cycle

TBD

60

TBD

55

mA

Operating Current

( Burst Mode)

ICC4

IOL=0mA ,tCC= tCC(min),

Page Burst, All Banks activated. DQ,DM,DQS inputs changing

twice per clock cycle. Address and control inputs changing

once per clock.

TBD

200

TBD

170

mA

Refresh Current

ICC5

tRC

≥ tRFC

TBD

160

TBD

165

mA

Self Refresh Current

ICC6

CKE

≤ 0.2V

TBD

8

TBD

8

mA

Operating Current

(4Bank interleaving)

ICC7

Burst Length=4 tRC

≥ tRC(min). IOL=0mA, tCC= tCC(min).

DQ,DM,DQS inputs changing twice per clock cycle. Address

and control inputs changing once per clock cycle

TBD

350

TBD

320

mA

8.8 DC characteristics

8.7 OCD default characteristics

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