10

S25FL Family (Serial Peripheral Interface)

30167A+1 June 9, 2004

P r el i m i n a r y

I n fo r m a t i o n

Protection Modes

The SPI memory device boasts the following data protection mechanisms:

All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its

reset state by the following events:

—Power-up

— Write Disable (WRDI) instruction completion

— Write Status Register (WRSR) instruction completion

— Page Program (PP) instruction completion

— Sector Erase (SE) instruction completion

— Bulk Erase (BE) instruction completion

The Block Protect (BP1, BP0) bits allow part of the memory to be configured

as read-only. This is the Software Protected Mode (SPM).

The Write Protect (W#) signal works in cooperation with the Status Register

Write Disable (SRWD) bit to enable write-protection. This is the Hardware

Protected Mode (HPM).

Program, Erase and Write Status Register instructions are checked to verify

that they consist of a number of clock pulses that is a multiple of eight, before

they are accepted for execution.

Table 1. Protected Area Sizes (S25FL002D).

Table 2. Protected Area Sizes (S25FL001D).

Note:The device is ready to accept a Bulk Erase (BE) instruction, if and only if, both Block Protect (BP1 and BP0) are 0.

Hold Condition Modes

The Hold (HOLD#) signal is used to pause any serial communications with the

device without resetting the clocking sequence. Hold (HOLD#) signal gates the

clock input to the device. However, taking this signal Low does not terminate any

Write Status Register, Program or Erase Cycle that is currently in progress.

Protected

Memory

Area

Status Register Content

Memory Content

BP1 Bit

BP0 Bit

Protected Area

Unprotected Area

0%

0

0

none

00000–3FFFF

25%

0

1

30000–3FFFF

00000–2FFFF

50%

1

0

20000–3FFFF

00000–1FFFF

100%

1

1

00000–3FFFF

none

Protected

Memory

Area

Status Register Content

Memory Content

BP1 Bit

BP0 Bit

Protected Area

Unprotected Area

0%

0

0

none

00000–1FFFF

25%

0

1

18000–1FFFF

00000–17FFF

50%

1

0

10000–1FFFF

00000–0FFFF

100%

1

1

00000–1FFFF

none