 Semiconductor Components Industries, LLC, 2005

January, 2005 − Rev. 11

1

Publication Order Number:

MUN2211T1/D

MUN2211T1 Series

Preferred Devices

Bias Resistor Transistors

NPN Silicon Surface Mount Transistors

with Monolithic Bias Resistor Network

This new series of digital transistors is designed to replace a single

device and its external resistor bias network. The BRT (Bias Resistor

Transistor) contains a single transistor with a monolithic bias network

consisting of two resistors; a series base resistor and a base−emitter

resistor. The BRT eliminates these individual components by

integrating them into a single device. The use of a BRT can reduce

both system cost and board space. The device is housed in the

SC−59 package which is designed for low power surface

mount applications.

modified gull−winged leads absorb thermal stress during soldering

eliminating the possibility of damage to the die.

Use the Device Number to order the 7 inch/3000 unit reel.

Rating

Symbol

Value

Unit

Collector-Base Voltage

50

Vdc

Collector-Emitter Voltage

50

Vdc

Collector Current

100

mAdc

THERMAL CHARACTERISTICS

Characteristic

Symbol

Max

Unit

Total Device Dissipation

Derate above 25°C

230 (Note 1)

338 (Note 2)

1.8 (Note 1)

2.7 (Note 2)

mW

°C/W

Thermal Resistance −

Junction-to-Ambient

540 (Note 1)

370 (Note 2)

°C/W

Thermal Resistance −

Junction-to-Lead

264 (Note 1)

287 (Note 2)

°C/W

Junction and Storage

Temperature Range

−55 to +150

°C

Maximum ratings are those values beyond which device damage can occur.

Maximum ratings applied to the device are individual stress limit values (not

normal operating conditions) and are not valid simultaneously. If these limits are

exceeded, device functional operation is not implied, damage may occur and

reliability may be affected.

1. FR−4 @ Minimum Pad.

2. FR−4 @ 1.0 x 1.0 inch Pad.

SC−59

CASE 318D

STYLE 1

Preferred devices are recommended choices for future use

and best overall value.

NPN SILICON

BIAS RESISTOR

TRANSISTORS

3

1

2

PIN 3

COLLECTOR

(OUTPUT)

PIN 1

EMITTER

(GROUND)

PIN 2

BASE

(INPUT)

MARKING DIAGRAM

8x = Specific Device Code*

M = Date Code

8x M

DEVICE MARKING INFORMATION

*See specific marking information in the device marking table

on page 2 of this data sheet.

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION