MK2722

Sigma Designs Clock Source

MDS 2722 B

2

Revision 020802

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295 9800tel • www.icst.com

Pin Descriptions

Key: I = Input, TI = Tri-level input, O = output, P = power supply connection

Pin Assignment

Number

Name

Type

Description

1

VDD

I

Connect to +5V.

2

X2

XO

Crystal connection. Connect to 27 MHz crystal. Leave unconnected for clock input.

3

X1

XI

Crystal connection. Connect to 27 MHz crystal or clock.

4

VDD

P

Connect to +5V.

5

GND

P

Connect to ground.

6

BS1

I

Select 1 for BCLK. Determines BCLK outputs per table above. Internal pull-up.

7

ACLK

O

Audio Clock output. Determined by status of AS1, AS0 per table above.

8

AS0

TI

Select 0 for ACLK. Determines ACLK output per table above.

9

BCLK

O

BCLK output. Determined by status of BS1, BS0 per table above.

10

BCLK/2

O

BCLK divided by two output. Determined by status of BS1, BS0 per table above.

11

GND

P

Connect to ground.

12

AS1

I

Select 1 for ACLK. Determines ACLK output per table above. Internal pull-up.

13

VDD

P

Connect to +5V.

14

27M

O

27.0000 MHz buffered crystal clock output.

15

PD

I

Power Down. Active low. Clocks stop low. Internal pull-up.

16

BS0

I

Select 0 for BCLK. Determines BCLK outputs per table above. Internal pull-up.

1

16

2

3

4

15

14

13

VDD

GND

X2

VDD

AS1

16 pin narrow (150 mil) SOIC

5

6

7

8

12

11

10

9

AS0

X1

VDD

27M

BS0

GND

BCLK/2

BCLK

ACLK

BS1

PD

AS1

AS0

ACLK

pin 12

pin 8

pin 7

0

0

12.288

0

M

18.432

0

1

16.9344

1

0

11.2896

1

M

12.288

1

1

8.192

ACLK Decoding Table (MHz)

BS1

BS0

BCLK

BCLK/2

pin 6

pin 16

pin 9

pin 10

0

0

40.5

20.25

0

1

50

25

1

0

28.6364

14.3182

1

1

40

20

BCLK Decoding Table (MHz)