IN74HC4046AN datasheet(8/11 Pages) INTEGRAL

Part #	IN74HC4046AN

Description	PHASE-LOCKED LOOP

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Manufacturer	INTEGRAL [Integral Corp.]

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IN74HC4046A

8

Figure 6. Logic Diagram for Phase Comparators

Phase Comparator 1

This comparator is a simple XOR gate

similar to the IN74HC86. Its operation is similar to

an overdriven balanced modulator. To maximize

lock range the input frequencies must have a 50%

duty cycle. Typical input and output waveforms

are shown in Figure 7. The output of the phase

detector feeds the loop filter which averages the

output voltage. The frequency range upon which

the PLL will lock onto if initially out of lock is

defined as the capture range.The capture range

for phase detector 1 is dependent on the loop

filter design. The capture range can be as large

as the lock range, which is equal to the VCO

frequency range.

To see how the detector operates, refer to

Figure 7. When two square wave signals are

applied to this comparator, an output waveform

(whose duty cycle is dependent on the phase

difference between the two signals) results. As

the phase difference increases, the output duty

cycle increases and the voltage after the loop filter

increases. In order to achieve lock when the PLL

input frequency increases, the VCO input voltage

must increase and the phase difference between

COMPIN and SIGIN will increase. At an input

frequency equal to fmin, the VCO input is at 0 V

Figure 7. Typical Waveforms for PLL Using

Phase Comparator 1

This requires the phase detector output to

be grounded; hence, the two input signals must

be in phase. When the input frequency is fmax, the

VCO input must be VCC and the phase detector

inputs must be 180 degrees out of phase.

The XOR is more susceptible to locking onto

harmonics of the SIGIN than the digital phase

detector 2. For instance, a signal 2 times the VCO

frequency results in the same output duty cycle as

a signal equal to the VCO frequency. The

difference is that the output frequency of the 2f

example is twice that of the other example. The

loop filter and VCO range should be designed to

prevent locking on to harmonics.

Phase Comparator 2

This detector is a digital memory network. It

consists of four flip-flops and some gating logic, a

three state output and a phase pulse output as

shown in Figure 6. This comparator acts only on

the positive edges of the input signals and is

independent of duty cycle.

Phase comparator 2 operates in such a

way as to force the PLL into lock with 0 phase

difference between the VCO output and the signal

input positive waveform edges. Figure 8 shows

some typical loop waveforms. First assume that

SIGIN is leading the COMPIN. This means that the

VCO’s frequency must be increased to bring its

leding edge into proper phase alignment. Thus

the phase detector 2 output is set high. This will

cause the loop filter to charge up the VCO input,

increasing the VCO frequency. Once the leading

edge of the COMPIN is detected, the output goes

TRI-STATE holding the VCO input at the loop

filter voltage. If the VCO still lags the SIGIN then

the phase detector will again charge up the VCO

input for the time between the leading edges of

both waveforms.

If the VCO leads the SIGIN then when the

leading edge of the VCO is seen; the output of the

phase comparator goes low. This discharges the

loop filter until the leading edge of the SIGIN is

detected at which time the output disables itself

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