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CXD1944R Datasheet(PDF) 11 Page - Sony Corporation |
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CXD1944R Datasheet(HTML) 11 Page - Sony Corporation |
11 / 21 page –11– CXD1944R Name Size Type Description Physical-ID 6 R The address number of this node. Determined during Self-ID. R 1 R Indicates that this node is the root. CPS 1 R Cable power status. RHB 1 R/W Root Holding Bit. Attempts to become the root during next bus reset if set to “1”. IBR 1 R/W Initiate Bus Reset. Generates bus reset when possible after being set to “1”. Cleared after bus reset. GC 6 R/W Gap Count. Used to optimize gap time according to bus scale. SPD 2 R Indicates this node’s highest speed; 200Mbps when “01”, 100Mbps when “00”. NP 4 R Indicates the number of ports on this node. ASTAT(n) 2 R Indicates port n TPA status. 11 = Z, 01 = 1, 10 = 0, 00 = invalid BSTAT(n) 2 R Indicates port n TPB status. 11 = Z, 01 = 1, 10 = 0, 00 = invalid Ch(n) 1 R When the value is “1”, indicates that port n is the Child. “0” indicates Parent. Con(n) 1 R When the value is “1”, indicates that the active cable is connected to port n. P(n) Fast 1 R When the value is “1”, indicates that port n supports 200Mbps. LoopInt 1 R/W This is set to “1” when Tree-ID is not completed in time, which means that the bus may be forming a loop. CPStatInt 1 R/W Indicates a drop in cable power line voltage. CPStat 1 R Same as CPS. IDidIt 1 R Indicates that this node generates the last bus reset. More than one node may set this value. IllegalReq 1 R Indicates an illegal LReq is detected. ChipRev 4 R Indicates the chip revision number. Slow Pin 1 R Indicates XSLOW pin is set to LOW. Slow Bit 1 R/W When set to “1”, the node acts as a 100Mbps PHY. Default is “0”. ArbRstReq 1 R/W Initiate the arbitrated bus reset. Cleared after bus reset. Ping Timer 16 R 50MHz Ping Timer count. A count starts when a configuration packet is trans- mitted and stops when the first packet is received. The value may not be cleared until the next configuration packet is sent. |
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