IC62LV256

Integrated Circuit Solution Inc.

7

ALSR007-0A 10/5/2001

-45 ns

-70 ns

-100 ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

45

—

70

—

100

—

ns

CE to Write End

35

—

60

—

80

—

ns

Address Setup Time to Write End

25

—

60

—

80

—

ns

Address Hold from Write End

0

—

0

—

0

—

ns

Address Setup Time

0

—

0

—

0

—

ns

WE Pulse Width

25

—

55

—

60

—

ns

Data Setup to Write End

20

—

30

—

35

—

ns

Data Hold from Write End

0

—

0

—

0

—

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured

3. The internal write time is defined by the overlap of

CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

4. Tested with

OE HIGH.

AC WAVEFORMS

WRITE CYCLE NO. 1 (

WE

WE

WE

WE

DATA-IN VALID

DATA UNDEFINED

HIGH-Z

ADDRESS

CE

WE