IC62LV256

2

Integrated Circuit Solution Inc.

ALSR007-0A 10/5/2001

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

FEATURES

• Access time: 45, 70, 100 ns

• Low active power: 70 mW

• Low standby power

— 60 µW CMOS standby

• Fully static operation: no clock or refresh

required

• TTL compatible inputs and outputs

• Single 3.3V power supply

DESCRIPTION

The

static RAM. It is fabricated using

CMOS double-metal technology.

When

CE is HIGH (deselected), the device assumes a standby

mode at which the power dissipation is reduced to

20 µW (typical) with CMOS input levels.

Easy memory expansion is provided by using an active LOW

Chip Enable (

CE) input and an active LOW Output Enable (OE)

input. The active LOW Write Enable (

WE) controls both writing

and reading of the memory.

The IC62LV256 is pin compatible with other 32K x 8 SRAMs

in 300mil DIP and SOJ, 330mil SOP, and 8*13.4mm TSOP-1

packages.

32K x 8 LOW VOLTAGE STATIC RAM

FUNCTIONAL BLOCK DIAGRAM

A0-A14

CE

OE

WE

256 X 1024

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7