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ST7LITE3 Datasheet(PDF) 22 Page - STMicroelectronics |
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ST7LITE3 Datasheet(HTML) 22 Page - STMicroelectronics |
22 / 167 page ST7LITE3 22/167 7 SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. Main features ■ Clock Management – 1 MHz internal RC oscillator (enabled by op- tion byte) – 1 to 16 MHz or 32kHz External crystal/ceramic resonator (selected by option byte) – External Clock Input (enabled by option byte) – PLL for multiplying the frequency by 8 or 4 (enabled by option byte) ■ Reset Sequence Manager (RSM) ■ System Integrity Management (SI) – Main supply Low voltage detection (LVD) with reset generation (enabled by option byte) – Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply (en- abled by option byte) 7.1 INTERNAL RC OSCILLATOR ADJUSTMENT The device contains an internal RC oscillator with an accuracy of 1% for a given device, temperature and voltage range (4.5V-5.5V). It must be calibrat- ed to obtain the frequency required in the applica- tion. This is done by software writing a 8-bit cali- bration value in the RCCR (RC Control Register) and in the bits [6:5] in the SICSR (SI Control Sta- tus Register). Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be load- ed in the RCCR. Predefined calibration values are stored in EEPROM for 3V and 5V VDD supply volt- ages at 25°C, as shown in the following table. 1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes containing also the RC calibration values which are read-accessible only in user mode. If all the EEPROM data or Flash space (including the RC calibration values locations) has been erased (after the read out protection removal), then the RC calibration values can still be obtained through these four addresses. For compatibility reasons with the SICSR register, CR[1:0] bits are stored in the 5th and 6th position of DEE1 and DEE3 addresses. Note: – See “ELECTRICAL CHARACTERISTICS” on page 129. for more information on the frequency and accuracy of the RC oscillator. – To improve clock stability, it is recommended to place a decoupling capacitor between the VDD and VSS pins. – These bytes are systematically programmed by ST, including on FASTROM devices. Conse- quently, customers intending to use FASTROM service must not use these bytes. – RCCR0 and RCCR1 calibration values will not be erased if the read-out protection bit is reset af- ter it has been set . See “Read out Protection” on page 13. Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Refer to application note AN1324 for information on how to calibrate the RC frequency using an ex- ternal reference signal. 7.2 PHASE LOCKED LOOP The PLL can be used to multiply a 1MHz frequen- cy from the RC oscillator or the external clock by 4 or 8 to obtain fOSC of 4 or 8 MHz. The PLL is ena- bled and the multiplication factor of 4 or 8 is select- ed by 2 option bits. – The x4 PLL is intended for operation with VDD in the 2.7V to 3.3V range – The x8 PLL is intended for operation with VDD in the 3.3V to 5.5V range Refer to Section 15.1 for the option byte descrip- tion. If the PLL is disabled and the RC oscillator is ena- bled, then fOSC = 1MHz. If both the RC oscillator and the PLL are disabled, fOSC is driven by the external clock. RCCR Conditions ST7LITE3 Addresses RCCRH0 VDD=5V TA=25°C fRC=1MHz DEE0h 1) (CR[9:2] bits) RCCRL0 DEE1h 1) (CR[1:0] bits) RCCRH1 VDD=3.3V TA=25°C fRC=1MHz DEE2h 1) (CR[9:2] bits) RCCRL1 DEE3h 1) (CR[1:0] bits) 1 |
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