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ST7LITE3 Datasheet(PDF) 23 Page - STMicroelectronics |
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ST7LITE3 Datasheet(HTML) 23 Page - STMicroelectronics |
23 / 167 page ST7LITE3 23/167 PHASE LOCKED LOOP (Cont’d) Figure 11. PLL Output Frequency Timing Diagram When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs the clock after a delay of tSTARTUP. When the PLL output signal reaches the operating frequency, the LOCKED bit in the SICSCR register is set. Full PLL accuracy (ACCPLL) is reached after a stabilization time of tSTAB (see Figure 11 and 13.3.4Internal RC Oscillator and PLL) Refer to section 7.6.4 on page 32 for a description of the LOCKED bit in the SICSR register. 7.3 REGISTER DESCRIPTION MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read / Write Reset Value: 0000 0000 (00h) Bits 7:2 = Reserved, must be kept cleared. Bit 1 = MCO Main Clock Out enable This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock. 0: MCO clock disabled, I/O port free for general purpose I/O. 1: MCO clock enabled. Bit 0 = SMS Slow Mode select This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock fOSC or fOSC/32. 0: Normal mode (fCPU = fOSC 1: Slow mode (fCPU = fOSC/32) RC CONTROL REGISTER (RCCR) Read / Write Reset Value: 1111 1111 (FFh) Bits 7:0 = CR[9:2] RC Oscillator Frequency Ad- justment Bits These bits must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. The application can store the correct value for each voltage range in EEPROM and write it to this register at start-up. 00h = maximum available frequency FFh = lowest available frequency These bits are used with the CR[1:0] bits in the SICSR register. Refer to section 7.6.4 on page 32 Note: To tune the oscillator, write a series of differ- ent values in the register until the correct frequen- cy is reached. The fastest method is to use a di- chotomy starting with 80h. 4/8 x freq. LOCKED bit set tSTAB tLOCK input tSTARTUP t 7 0 0 0 0 0 0 0 MCO SMS 7 0 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 1 |
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