SN74LS298

http://onsemi.com

3

LOGIC OR BLOCK DIAGRAM

S

CP

R

CP

R

CP

14

1

2

67

3

4

5

9

11

12

10

13

15

GND = PIN 8

= PIN NUMBERS

R

CP

R

CP

FUNCTIONAL DESCRIPTION

The LS298 is a high speed Quad 2-Port Register. It selects

four bits of data from two sources (ports)under the control

of a Common Select Input (S). The selected data is

transferred to the 4-bit output register synchronous with the

HIGH to LOW transition of the Clock input (CP). The 4-bit

output register is fully edge-triggered. The Data inputs (I)

and Select input (S) must be stable only one setup time prior

to the HIGH to LOW transition of the clock for predictable

operation.

TRUTH TABLE

INPUTS

OUTPUT

S

Q

I

I

X

L

I

h

X

H

h

X

I

L

h

X

h

H

L = LOW Voltage Level

H = HIGH Voltage Level

X = Don’t Care

I = LOW Voltage Level one setup time prior to the HIGH to LOW clock transition.

h = HIGH Voltage Level one setup time prior to the HIGH to LOW clock transition.