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SN74LS373DWR2 Datasheet(PDF) 2 Page - ON Semiconductor |
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SN74LS373DWR2 Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 8 page SN74LS373, SN74LS374 http://onsemi.com 2 CONNECTION DIAGRAM DIP (TOP VIEW) Data Inputs Latch Enable (Active HIGH) Input Clock (Active HIGH Going Edge) Input Output Enable (Active LOW) Input Outputs D0 - D7 LE CP OE O0 - O7 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. HIGH LOW (Note a) LOADING PIN NAMES NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual InLine Package. SN74LS373 SN74LS374 18 17 16 15 14 13 12 3 4 5 6 7 20 19 8 VCC OE O7 D7 D6 O6 D5 O5 D4 O0 D0 D1 O1 O2 D2 D3 910 O3 GND 12 O4 LE 18 17 16 15 14 13 12 3 4 5 6 7 20 19 8 VCC OE O7 D7 D6 O6 D5 O5 D4 O0 D0 D1 O1 O2 D2 D3 910 O3 GND 12 11 O4 CP 11 TRUTH TABLE LS373 Dn LE OE On H H L H L H L L X L L Q0 X X H Z* LS374 Dn LE OE On H L H L L L X X H Z* H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance * Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE). |
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