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SN54LV165J Datasheet(PDF) 1 Page - Texas Instruments |
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SN54LV165J Datasheet(HTML) 1 Page - Texas Instruments |
1 / 8 page SN54LV165, SN74LV165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCES007B – MARCH 1995 – REVISED APRIL 1996 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D EPIC™ (Enhanced-Performance Implanted CMOS) 2- µ Process D Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C D Typical VOHV (Output VOH Undershoot) < 2 V at VCC, TA = 25°C D ESDProtectionExceeds2000VPer MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 D Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs description The ’LV165 parallel-load, 8-bit shift registers are designed for 2.7-V to 5.5-V VCC operation. When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/ LD input. The ’LV165 feature a clock inhibit function and a complemented serial output QH. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/ LD is held high and clock inhibit (CLK INH) is held low. The functions of the CLK and CLK INH inputs are interchangeable. Since a low CLK input and a low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/ LD is held high. The parallel inputs to the register are enabled while SH/ LD is held low independently of the levels of CLK, CLK INH, or SER. The SN54LV165 is characterized for operation over the full military temperature range of –55 °C to 125°C. The SN74LV165 is characterized for operation from –40 °C to 85°C. FUNCTION TABLE INPUTS OPERATION SH/ LD CLK CLK INH OPERATION L X X Parallel load H HX Q0 H XH Q0 H L ↑ Shift H ↑ L Shift Copyright © 1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. EPIC is a trademark of Texas Instruments Incorporated. SN54LV165 ...J OR W PACKAGE SN74LV165 . . . D, DB, OR PW PACKAGE (TOP VIEW) 32 1 20 19 910 11 12 13 4 5 6 7 8 18 17 16 15 14 D C NC B A E F NC G H SN54LV165 . . . FK PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SH/LD CLK E F G H QH GND VCC CLK INH D C B A SER QH NC – No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. |
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