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TLC32040CN Datasheet(PDF) 9 Page - Texas Instruments |
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TLC32040CN Datasheet(HTML) 9 Page - Texas Instruments |
9 / 33 page TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 explanation of internal timing configuration (continued) The ability to advance or retard conversion timing is particularly useful for modem applications. This feature allows controlled changes in the A/D and D/A conversion timing. This feature can be used to enhance signal-to-noise performance, to perform frequency-tracking functions, and to generate nonstandard modem frequencies. If the transmit and receive sections are configured to be synchronous (see WORD/BYTE description), then both the low-pass and bandpass switched-capacitor filter clocks are derived from TX counter A. Also, both the D/A and A/D conversion timing are derived from the TX counter A and TX counter B. When the transmit and receive sections are configured to be synchronous, the RX counter A, RX counter B, RA register, RA’ register, and RB registers are not used. |
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