DM8108
8 port 10/100M Fast Ethernet Switching Controller
Preliminary
7
Version: DM8108-DS-P02
November 25, 1999
Pin Description (continued)
Please refer to the “Strap pin default value after reset section” for the detail description of the
Strap pins.
DRAM Interface
Pin No.
Pin Name
I/O
Description
139 – 146,
148 – 155,
157 – 164,
166 – 173
MD(31:0)
I/O
DRAM data lines 31 – 0
183 – 184,
186 – 189,
191 – 195
MA(10:0)
I/O
DRAM address lines 10-0; strap pins during reset
MA9: 0= enable limit4, 1=disbale limit 4
MA8: DRAM size selection; 0= 1M, 1=2M
MA7-0: Auto-negotiation enable for port 7-0; 0= enabled
177
SRAS*
O
Row address strobe for SDRAM
178
SDCAS*
O
Column address strobe for SDRAM
180
SDWE*
O
Write cycle indication, internally pulled up
182
SDQM
O
Data Mask for SDRAM
179
SDCS*
O
Chip select for SDRAM
Expansion Bus
Pin No.
Pin Name
I/O
Description
204
RXDVCLK
I/O
Expansion port’s receiving data valid
208 – 205
RXD8[3:0]
I/O
Expansion port’s receive data input
197
TXENCLK
I/O
Expansion port’s transmit enable output
202 – 199
TXD8[3:0]
I/O
Expansion port’s transmit data output
Strap pins during reset:
TXD8[2:0] = device # setting
TXD8[3]
= dram timing
LED Interface
Pin No.
Pin Name
I/O
Description
2
LEDCLK
O
LED data clock
4
LEDD
O
LED data: active low. Data stream that contains LED indicators per
port. The data is shifted out and should be qualified by LDSTB* to
clock into external registers to drive LEDs.
Strap pin during reset:
0: expansion port with fast speed
1: expansion port with lower apees
3
LDSTB
I/O
LED data strobe: active high. Used to strobe the LD into an external
register
Strap pin during reset:
0: force link
1: link detection through serial MII
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