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NCP1217P133 Datasheet(PDF) 11 Page - ON Semiconductor |
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NCP1217P133 Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 18 page NCP1217, NCP1217A http://onsemi.com 11 Power P1 Power P2 Power P3 Figure 20. Output Pulses at Various Power Levels (X = 5.0 ms/div) P1 t P2 t P3 Figure 21. The Skip Cycle Takes Place at Low Peak Currents which Guarantees Noise−Free Operation 315.40 U 882.70 U 1.450 M 2.017 M 2.585 M 300 M 200 M 100 M 0 MAX PEAK CURRENT SKIP CYCLE CURRENT LIMIT Sufficient margin shall be kept between normal Pin1 level and the latchoff point in order to avoid false triggering. Ramp Compensation Ramp compensation is a known mean to cure subharmonic oscillations. These oscillations take place at half the switching frequency and occur only during Continuous Conduction Mode (CCM) with a duty−cycle greater than 50%. To lower the current loop gain, one usually injects between 50 and 100% of the inductor down−slope. Figure 22 depicts how internally the ramp is generated. |
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