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UPD780034A Datasheet(PDF) 10 Page - NEC |
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UPD780034A Datasheet(HTML) 10 Page - NEC |
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10 / 90 page  µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A) 10 Data Sheet U16369EJ1V0DS Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name A1 NC C1 P52/A10 E1 P57/A15 G1 P33/SCL0Note 1 J1 NC A2 P46/AD6 C2 P53/A11 E2 VDD0 G2 P32/SDA0Note 1 J2 P36/SCK31Note2 A3 P44/AD4 C3 P45/AD5 E3 P54/A12 G3 P20/SI30 J3 NC A4 P41/AD1 C4 P42/AD2 E4 − G4 P21/SO30 J4 P25/ASCK0 A5 P67/ASTB C5 P64/RD E5 − G5 P24/TxD0 J5 NC A6 P65/WR C6 P73/TI51/TO51 E6 − G6 VDD1 J6 P17/ANI7 A7 P74/PCL C7 P03/INTP3/ADTRG E7 P00/INTP0 G7 P16/ANI6 J7 P12/ANI2 A8 NC C8 P01/INTP1 E8 XT1 G8 AVDD J8 P13/ANI3 A9 NC C9 VSS1 E9 X2 G9 NC J9 NC B1 P51/A9 D1 P55/A13 F1 P30 H1 P34/SI31Note 2 B2 P47/AD7 D2 P56/A14 F2 P31 H2 P35/SO31Note 2 B3 P43/AD3 D3 P50/A8 F3 VSS0 H3 P23/RxD0 B4 P40/AD0 D4 NC F4 − H4 P22/SCK30 B5 P66/WAIT D5 − F5 − H5 AVSS B6 P75/BUZ D6 − F6 − H6 P15/ANI5 B7 P72/TI50/TO51 D7 P02/INTP2 F7 P14/ANI4 H7 P11/ANI1 B8 P71/TI01 D8 VPP F8 RESET H8 P10/ANI0 B9 P70/TI00/TO0 D9 X1 F9 XT2 H9 AVREF Notes 1. SDA0 and SCL0 are incorporated only in the µPD78F0034BY Subseries. 2. SI31, SO31, and SCK31 are incorporated only in the µPD78F0034B Subseries. Cautions 1. Connect the VPP pin directly to VSS0 or VSS1 in normal operation mode. 2. Connect the AVSS pin to VSS0. Remarks 1. When the µPD78F0034B, 78F0034BY, 78F0034B(A), and 78F0034BY(A) are used in application fields that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended. 2. The special grade version of the 73-pin plastic FBGA (9 x 9) is not provided. • 73-pin plastic FBGA (9 x 9) Top View Bottom View JHGFEDCBA ABCDEFGHJ 9 8 7 6 5 4 3 2 1 Index mark |
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