ADM1487

Rev. PrC

–5–

R

R

A

A

Figure 1. Driver DC Load Test Circuit

3V

DE

DI

RO

D

R

15pF

A

B

A

B

Figure 2. Driver/Receiver Timing Test Circuit

DI

B

A

V

0V

90%

10%

90%

10%

3V

0V

1.5V

t

DPLH

Figure 3. Driver Propagation Delays

RO

A

B

1.5V

t

RPLH

t

RPHL

Figure 4. Receiver Propagation Delays

ADM1487 TEST CIRCUITS AND TIMING

S1

S2

TEST

POINT

15pF

500V

OUTPUT

UNDER

TEST

Figure 5. Test Load for Driver Enable/Disable Time Test

3V

0V

DE

A, B

A, B

OUTPUT NORMALLY LOW

OUTPUT NORMALLY HIGH

1.5V

2.3V

2.3

V

5V

Figure 6. Driver Enable and Disable Times

RO

TEST

POINT

1kV

1kV

S1

S2

15pF

Figure 7. Test Load for Receiver Enable/Disable Time Test

OUTPUT NORMALLY LOW

OUTPUT NORMALLY HIGH

3V

0V

RE

RO

RO

1.5

V

0.5V

0.5V

0V

1.5

V

5V

1.5

V

5V

Figure 8. Receiver Enable and Disable Delay Times

PRELIMINARY TECHNICAL DATA