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XRT86L30IB Datasheet(PDF) 4 Page - Exar Corporation |
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XRT86L30IB Datasheet(HTML) 4 Page - Exar Corporation |
4 / 284 page XRT86L30 PRELIMINARY REV. P1.0.1 SINGLE T1/E1/J1 FRAMER/LIU COMBO I LIST OF PARAGRAPHS 1.0 PIN LIST .................................................................................................................................................10 2.0 PIN DESCRIPTIONS ..............................................................................................................................11 3.0 MICROPROCESSOR INTERFACE BLOCK ..........................................................................................24 3.0.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ....................................................................................... 24 3.1 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .................................................................. 27 3.2 MOTOROLA MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) .......................................................... 29 3.2.1 DMA READ/WRITE OPERATIONS .............................................................................................................................. 31 3.3 MEMORY MAPPED I/O ADDRESSING ............................................................................................................ 33 3.4 DESCRIPTION OF THE CONTROL REGISTERS ............................................................................................ 34 3.4.1 REGISTER DESCRIPTIONS ......................................................................................................................................... 40 3.5 PROGRAMMING THE LINE INTERFACE UNIT (LIU SECTION) ................................................................... 124 3.6 THE INTERRUPT STRUCTURE WITHIN THE FRAMER ............................................................................... 143 3.6.1 CONFIGURING THE INTERRUPT SYSTEM, AT THE FRAMER LEVEL .................................................................. 146 4.0 GENERAL DESCRIPTION AND INTERFACE .....................................................................................149 4.1 PHYSICAL INTERFACE .................................................................................................................................. 149 4.2 R3 TECHNOLOGY (RELAYLESS / RECONFIGURABLE / REDUNDANCY) ................................................ 150 4.2.1 LINE CARD REDUNDANCY ....................................................................................................................................... 150 4.2.2 TYPICAL REDUNDANCY SCHEMES ........................................................................................................................ 150 4.2.3 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 150 4.2.4 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 150 4.2.5 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY ..................................................................................... 151 4.3 POWER FAILURE PROTECTION ................................................................................................................... 152 4.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ................................................................................ 152 4.5 NON-INTRUSIVE MONITORING ..................................................................................................................... 152 4.6 T1/E1 SERIAL PCM INTERFACE ................................................................................................................... 153 4.7 T1/E1 FRACTIONAL INTERFACE .................................................................................................................. 154 4.8 T1/E1 TIME SLOT SUBSTITUTION AND CONTROL ..................................................................................... 155 4.9 ROBBED BIT SIGNALING/CAS SIGNALING ................................................................................................. 156 4.10 OVERHEAD INTERFACE .............................................................................................................................. 158 4.11 FRAMER BYPASS MODE ............................................................................................................................. 159 4.12 HIGH-SPEED NON-MULTIPLEXED INTERFACE ........................................................................................ 160 4.13 HIGH-SPEED MULTIPLEXED INTERFACE ................................................................................................. 161 5.0 LOOPBACK MODES OF OPERATION ............................................................................................... 162 5.1 LIU PHYSICAL INTERFACE LOOPBACK DIAGNOSTICS ............................................................................ 162 5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 162 5.1.2 REMOTE LOOPBACK ................................................................................................................................................ 162 5.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 163 5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 163 5.1.5 FRAMER REMOTE LINE LOOPBACK ...................................................................................................................... 163 5.1.6 FRAMER PAYLOAD LOOPBACK ............................................................................................................................. 164 5.1.7 FRAMER LOCAL LOOPBACK ................................................................................................................................... 164 6.0 HDLC CONTROLLERS AND LAPD MESSAGES ...............................................................................165 6.1 PROGRAMMING SEQUENCE FOR SENDING LESS THAN 96-BYTE MESSAGES .................................... 165 6.2 PROGRAMMING SEQUENCE FOR SENDING LARGE MESSAGES ........................................................... 165 6.3 PROGRAMMING SEQUENCE FOR RECEIVING LAPD MESSAGES ........................................................... 165 6.4 SS7 (SIGNALING SYSTEM NUMBER 7) FOR ESF IN DS1 ONLY ................................................................ 166 6.5 DS1/E1 DATALINK TRANSMISSION USING THE HDLC CONTROLLERS ................................................. 167 6.6 TRANSMIT BOS (BIT ORIENTED SIGNALING) PROCESSOR ..................................................................... 167 6.6.1 DESCRIPTION OF BOS .............................................................................................................................................. 167 6.6.2 PRIORITY CODEWORD MESSAGE .......................................................................................................................... 167 6.6.3 COMMAND AND RESPONSE INFORMATION .......................................................................................................... 167 6.7 TRANSMIT MOS (MESSAGE ORIENTED SIGNALING) PROCESSOR ........................................................ 168 6.7.1 DISCUSSION OF MOS ............................................................................................................................................... 168 6.7.2 PERIODIC PERFORMANCE REPORT ...................................................................................................................... 168 6.7.3 TRANSMISSION-ERROR EVENT .............................................................................................................................. 169 6.7.4 PATH AND TEST SIGNAL IDENTIFICATION MESSAGE ......................................................................................... 169 6.7.5 FRAME STRUCTURE ................................................................................................................................................. 169 6.7.6 FLAG SEQUENCE ...................................................................................................................................................... 169 6.7.7 ADDRESS FIELD ........................................................................................................................................................ 170 6.7.8 ADDRESS FIELD EXTENSION BIT (EA) ................................................................................................................... 170 |
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