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ICS853014BGLFT Datasheet(PDF) 3 Page - Integrated Circuit Systems |
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ICS853014BGLFT Datasheet(HTML) 3 Page - Integrated Circuit Systems |
3 / 17 page 853014BG www.icst.com/products/hiperclocks.html REV. C MAY 13, 2005 3 Integrated Circuit Systems, Inc. ICS853014 LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE TABLE 3B. CLOCK INPUT FUNCTION TABLE s t u p n Is t u p t u O N E nL E S _ K L Ce c r u o S d e t c e l e S4 Q : 0 Q4 Q n : 0 Q n 10 0 K L C P n , 0 K L C PW O L ; d e l b a s i DH G I H ; d e l b a s i D 11 1 K L C P n , 1 K L C PW O L ; d e l b a s i DH G I H ; d e l b a s i D 00 0 K L C P n , 0 K L C Pd e l b a n Ed e l b a n E 01 1 K L C P n , 1 K L C Pd e l b a n Ed e l b a n E n i n w o h s s a e g d e k c o l c t u p n i g n il l a f a g n i w o ll o f d e l b a n e r o d e l b a s i d e r a s t u p t u o k c o l c e h t , s e h c t i w s N E n r e t f A r u g i F e . 1 s a s t u p n i 1 K L C P n , 1 K L C P d n a 0 K L C P n , 0 K L C P e h t f o n o i t c n u f a e r a s t u p t u o e h t f o e t a t s e h t , e d o m e v i t c a e h t n I n i d e b i r c s e d . B 3 e l b a T s t u p n Is t u p t u O e d o M t u p t u O o t t u p n Iy t i r a l o P 1 K L C P r o 0 K L C P1 K L C P n r o 0 K L C P n4 Q : 0 Q4 Q n : 0 Q n 01 W O LH G I Hl a i t n e r e f f i D o t l a i t n e r e f f i Dg n i t r e v n I n o N 10 H G I HW O Ll a i t n e r e f f i D o t l a i t n e r e f f i Dg n i t r e v n I n o N 01 E T O N ; d e s a i BW O LH G I Hl a i t n e r e f f i D o t d e d n E e l g n i Sg n i t r e v n I n o N 11 E T O N ; d e s a i BH G I HW O Ll a i t n e r e f f i D o t d e d n E e l g n i Sg n i t r e v n I n o N 1 E T O N ; d e s a i B0 H G I HW O Ll a i t n e r e f f i D o t d e d n E e l g n i Sg n i t r e v n I 1 E T O N ; d e s a i B1 W O LH G I Hl a i t n e r e f f i D o t d e d n E e l g n i Sg n i t r e v n I . " s l e v e L d e d n E e l g n i S t p e c c A o t t u p n I l a i t n e r e f f i D e h t g n i r i W " , n o i t c e s n o i t a m r o f n I n o i t a c il p p A e h t o t r e f e r e s a e l P : 1 E T O N FIGURE 1. nEN TIMING DIAGRAM Enabled Disabled nPCLK0, nPCLK1 PCLK0, PCLK1 nEN nQ0:nQ4 Q0:Q4 |
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