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HM6264ALP-10 Datasheet(PDF) 9 Page - Hitachi Semiconductor

Part # HM6264ALP-10
Description  8192-word x 8-bit High Speed CMOS Static RAM
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Manufacturer  HITACHI [Hitachi Semiconductor]
Direct Link  http://www.renesas.com/eng
Logo HITACHI - Hitachi Semiconductor

HM6264ALP-10 Datasheet(HTML) 9 Page - Hitachi Semiconductor

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HM6264A Series
HM6264A Series
Low VCC Data Retention
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only L/LL-version.
Parameter
Symbol
Min
Typ
Max
Unit
Test Condition
VCC for data retention
VDR
2.0
V
CS1
≥ V
CC – 0.2 V,
CS2
≥ V
CC– 0.2 V, or
CS2
≤ 0.2 V
Data retention current
ICCDR
—1*1
50*1
µA
VCC = 3.0 V,
—1*2
25*2
Chip deselect to data
t
CDR
0
ns
See retention waveform
retention time
Operation recovery time
tR
t
RC
*3
ns
See retention waveform
Notes:
1. VIL min = –0.3 V, 20 µA max at Ta = 0 to 40°C. These characteristics are guaranteed only for
the L-version.
2. VIL min = –0.3 V, 10 µA max at Ta = 0 to 40°C. These characteristics are guaranteed only for
the LL-version.
3. tRC = Read cycle time.
Low VCC Data Retention Waveform (1) (CS1 Controlled)
CS1
≥ V
CC – 0.2 V,
CS2
≥ V
CC – 0.2 V, or
0 V
≤ CS2 ≤ 0.2 V, 0 V ≤ Vin
In data retention mode, CS2 controls the address,
WE, CS1, OE, and the Din buffer. If CS2 controls
data retention mode, Vin (for these inputs) can be
in the high impedance state. If CS1 controls the
data retention mode, CS2 must satisfy either
CS2
≥ V
CC – 0.2 V or CS2 ≤ 0.2 V. The other
input levels (address,
WE, OE, I/O) can be in the
high impedance state.
tCDR
tR
Data retention mode
CS1
≥ V
CC – 0.2 V
VCC
4.5 V
2.2 V
VDR
0 V
CS1


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