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APPLICATIONS

DESCRIPTION

4 mA

SN65LVDS16, SN65LVP16

Q

A

GC

Y

Z

EN

4 mA

SN65LVDS17, SN65LVP17

Q

A

Y

Z

EN

B

SN65LVDS16, SN65LVP16

SN65LVDS17, SN65LVP17

SLLS625B – SEPTEMBER 2004 – REVISED NOVEMBER 2005

2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

•

2-mm × 2-mm Small-Outline

No-Lead Package

•

Low-Voltage PECL Input and Low-Voltage

PECL or LVDS Outputs

•

Clock Rates to 2 GHz

•

PECL-to-LVDS Translation

– 140-ps Output Transition Times

•

Clock Signal Amplification

– 0.11 ps Typical Intrinsic Phase Jitter

– Less than 630 ps Propagation Delay Times

•

2.5-V or 3.3-V Supply Operation

These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain

outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on

the SN65LVx16) and fully differential inputs on the SN65LVx17.

The SN65LVx16 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV

Q on the SN65LVx17 defaults to 575 mV as well.

All devices are characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2004–2005, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.