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TMS28F033 Datasheet(PDF) 8 Page - Texas Instruments |
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TMS28F033 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 52 page TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 operation (continued) Table 4. Command-State-Machine Codes for Device Mode Selection COMMAND CODE ON DQ0 – DQ7† DEVICE MODE 02h Block-erase setup of overlay block 04h Program setup of overlay block 06h Enable/disable overlay block for reads 0Dh Block-erase confirm of overlay block 20h Block-erase setup of main array 40h Program setup of main array 50h Clear status register 60h Enable/disable low-power programming 70h Read status register 90h Silicon signature selection 96h Load device-configuration register D0h Block-erase confirm of main array F0h Reduced power FFh Read array † DQ0 is the least significant bit. DQ8 – DQ31 can be any valid 2-state level. command definition Once a specific command code has been entered, the WSM executes an internal algorithm that generates the necessary timing signals to program, erase, and verify data. See Table 5 for the CSM command definitions and the data for each of the bus cycles. See Table 6 for the addresses required to access the algorithm selection codes. |
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