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TMS28F033 Datasheet(PDF) 11 Page - Texas Instruments

Part # TMS28F033
Description  4194304-BIT SYNCHRONOUS FLASH MEMORY
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS28F033 Datasheet(HTML) 11 Page - Texas Instruments

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TMS28F033
4194304-BIT
SYNCHRONOUS FLASH MEMORY
SMJS833 – NOVEMBER 1997
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
status register (continued)
Table 7. Status-Register Bit Definitions and Functions
STATUS
BIT
FUNCTION
DATA
COMMENTS
SB7
Write-State-Machine (WSM)
Status
1 = Ready
0 = Busy
If SB7 = 0 (busy), the WSM has not completed an
erase or programming operation. If SB7 = 1
(ready), other operations can be performed.
SB6
Reserved
0
SB5
(DCR4 = 0)
Operation Status
(OS)
1 = Commands/operations not
successful
0 = Commands/operations
successful
The WSM sets the OS bit high (SB5 = 1) after an
illegal command has been issued, an error has
occurred while erasing a block, or as the result of
an error while programming a word. If all past
operations have completed successfully, then the
OS bit remains low (SB5 = 0); however, the WSM
cannot clear this bit.
SB5
(DCR4 = 1)
Erase Status
(ES)
1 = Block-erase error
0 = Block-erase good
SB5 = 0 indicates that a block-erase has been
successful. SB5 = 1 indicates that an erase error
has occurred. In this case, the WSM has
completed the maximum erase pulses determined
by the internal algorithm, but this was insufficient
to completely erase the device.
SB4
(DCR4 = 0)
Low Regulator Voltage
Status (LRVS)
1 = LRV asserted
0 = LRV not asserted
The LRVS bit is set high (SB4 = 1) when the LRV
input is asserted during an erase or program
command. The clear-status-register command
clears the LRVS bit (SB4 = 0).
SB4
(DCR4 = 1)
Program Status
(PS)
1 = Program error
0 = Program good
SB4 = 0 indicates successful programming has
occurred at the addressed location. SB4 = 1
indicates that the WSM was unable to correctly
program the addressed location.
SB3
VPP Status
(VPPS)
1 = Program abort:
VPP range error
0= VPP good
SB3 provides information on the status of VPP
during programming and erasing. If VPP is lower
than VPPL after a program or erase command has
been issued, SB3 is set to a 1 to indicate that the
operation is aborted.
SB2
Low-Power Mode
(LPM)
1 = Byte-program
0 = Word-program
When the LPM bit is set high (SB2 = 1), the WSM
programs each word in byte increments. When the
LPM bit is low (SB2 = 0), the WSM programs in
word (x32 or x16) increments.
SB1
Overlay-Block-Enable Bit
(OBEB)
1 = Overlay block can be
enabled
0 = Overlay block disabled
When the OBEB bit, which is VPP-independent, is
set (SB1 = 1), the overlay block can be enabled for
reads. When the OBEB bit is low (SB1 = 0), the
overlay block is disabled for reads.
SB0
Overlay-Block Status
(OBS)
1 = Overlay block enabled
0 = Overlay block disabled
When the OBS bit, with VPP ≥ VPPH, is set
(SB0 = 1), the overlay block is enabled for reads.
When the OBS bit is cleared (SB0 = 0), the overlay
block is disabled for reads.
device configuration register (DCR)
The DCR is a user-loaded register that determines many of the device functions (see Table 8). Sixteen
configurable bits (DCR0 – DCR7 and DCR24 – DCR31 with DCR26 – 27 reserved) can be set by using the
load-DCR CSM command (96h) (see Table 5). The current value of the DCR can be read with CSM command
90h, provided A1 is set to VIH and A0 is set to VIL (see Table 6).


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