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GS881Z32BT-333 Datasheet(PDF) 28 Page - GSI Technology |
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GS881Z32BT-333 Datasheet(HTML) 28 Page - GSI Technology |
28 / 39 page GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D) Rev: 1.04 10/2004 28/39 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. ID Register Contents Die Revision Code Not Used I/O Configuration GSI Technology JEDEC Vendor ID Code Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 X X X X 0 000000 0000010 00 0 0 0 1 1 0 1 1 0 0 1 1 x32 X X X X 0 000000 0000011 00 0 0 0 1 1 0 1 1 0 0 1 1 x18 X X X X 0 000000 0000010 10 0 0 0 1 1 0 1 1 0 0 1 1 |
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