11

COMMERCIALTEMPERATURERANGE

BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36

NOTE:

1. X register holds the offset for

AE; Y register holds the offset for AF.

2. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.

3. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.

4. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.

— PRESET VALUES

ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith

oneofthefivepresetvalueslistedinTable1,theflagselectinputsmustbeHIGH

or LOW during a reset. For example, to load the preset value of 64 into X and

Y, FS0, FS1 and FS2 must be HIGH when

RS1returnsHIGH. Fortherelevant

preset value loading timing diagram, see Figure 3.

— PARALLEL LOAD FROM PORT A

ToprogramtheXandYregistersfromPortA,performaResetwithFS2HIGH

or LOW and FS0 and FS1 LOW during the LOW-to-HIGH transition of

RS1.

The state of FS2 at this point of reset will determine whether the parallel

programming method has Interspersed Parity or Non-Interspersed Parity.

Refer to Table 1 for Flag Programming Flag Offset setup. It is important to note

that once parallel programming has been selected during a Master Reset by

holding both FS0 & FS1 LOW, these inputs must remain LOW during all

subsequent FIFO operation. They can only be toggled HIGH when future

Master Resets are performed and other programming methods are desired.

After this reset is complete, the first two writes to the FIFO do not store data

in RAM. The first two write cycles load the offset registers in the order Y, X. On

thethirdwritecycletheFIFOisreadytobeloadedwithadataword. SeeFigure

5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag

Offset Values after Reset (IDT Standard and FWFT modes), for a detailed

timingdiagram.ForNon-InterspersedParitymodethePortAdatainputsused

bytheOffsetregistersare(A13-A0),(A14-A0),or(A15-A0)fortheIDT72V3683,

IDT72V3693, or IDT72V36103, respectively. For Interspersed Parity mode

the Port A data inputs used by the Offset registers are (A14-A9, A7-A0), (A15-

A9, A7-A0), or (A16-A9, A7-A0) for the IDT72V3683, IDT72V3693, or

IDT72V36103, respectively. The highest numbered input is used as the most

significantbitofthebinarynumberineachcase. Validprogrammingvaluesfor

the registers range from 1 to 16,380 for the IDT72V3683; 1 to 32,764 for the

IDT72V3693;and1to65,532fortheIDT72V36103. Afteralltheoffsetregisters

are programmed from Port A, the FIFO begins normal operation.

INTERSPERSED PARITY

Interspersed Parity is selected during a Master Reset of the FIFO. Refer

to Table 1 for the set-up configuration of Interspersed Parity. The Interspersed

Parityfunctionallowstheusertoselectthelocationoftheparitybitsintheword

loaded into the parallel port (A0-An) during programming of the flag offset

values. If Interspersed Parity is selected then during parallel programming of

the flag offset values, the device will ignore data line A8. If Non-Interspersed

Parity is selected then data line A8 will become a valid bit. If Interspersed Parity

isselectedserialprogrammingoftheoffsetvaluesisnotpermitted,onlyparallel

programming can be done.

— SERIAL LOAD

ToprogramtheXandYregistersserially,initiateaResetwithFS2LOW,FS0/

SDLOWandFS1/

SENHIGHduringtheLOW-to-HIGHtransitionofRS1. After

this reset is complete, the X and Y register values are loaded bit-wise through

the FS0/SD input on each LOW-to-HIGH transition of CLKA that the FS1/

SEN

input is LOW. There are 28-, 30- or 32-bit writes needed to complete the

programmingfortheIDT72V3683,IDT72V3693ortheIDT72V36103,respec-

tively. The two registers are written in the order Y, X. Each register value can

be programmed from 1 to 16,380 (IDT72V3683), 1 to 32,764 (IDT72V3693)

or 1 to 65,532 (IDT72V36103).

When the option to program the offset registers serially is chosen, the Full/

Input Ready (

FF/IR)flagremainsLOWuntilallregisterbitsarewritten. FF/IR

is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded

to allow normal FIFO operation.

See Figure 6, Serial Programming of the Almost-Full Flag and Almost-

Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).

FIFO WRITE/READ OPERATION

ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect

(

CSA)andPortAWrite/Readselect(W/RA). TheA0-A35linesareintheHigh-

impedance state when either

CSA or W/RA is HIGH. The A0-A35 lines are

active outputs when both

CSA and W/RA are LOW.

Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH

transition of CLKA when

CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is

LOW, and

FF/IRisHIGH(seeTable2). FIFOwritesonPortAareindependent

of any concurrent reads on Port B.

The Port B control signals are identical to those of Port A with the exception

thatthePortBWrite/Readselect(

W/RB)istheinverseofthePortAWrite/Read

select (W/

RA). ThestateofthePortBdata(B0-B35)linesiscontrolledbythe

Port B Chip Select (

CSB) and Port B Write/Read select (W/RB). The B0-B35

linesareinthehigh-impedancestatewheneither

CSBisHIGHorW/RBisLOW.

The B0-B35 lines are active outputs when

CSB is LOW and W/RB is HIGH.

DataisreadfromtheFIFOtotheB0-B35outputsbyaLOW-to-HIGHtransition

of CLKB when

CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and

FS2

FS1/

SEN

FS0/SD

RS1

HH

H

↑

64

HH

L

↑

16

HL

H

↑

8

LH

H

↑

256

LL

H

↑

1,024

LH

L

↑

Serial programming via SD

HLL

↑

LL

L

↑

TABLE 1 — FLAG PROGRAMMING