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IDT72V36103L15PF Datasheet(PDF) 1 Page - Integrated Device Technology

Part # IDT72V36103L15PF
Description  3.3 VOLT CMOS SyncFIFO WITH BUS-MATCHING
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72V36103L15PF Datasheet(HTML) 1 Page - Integrated Device Technology

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1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
COMMERICAL TEMPERATURE RANGE
3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING
16,384 x 36
32,768 x 36
65,536 x 36
IDT72V3683
IDT72V3693
IDT72V36103
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO
 isatrademarkofIntegratedDeviceTechnology,Inc.
NOVEMBER 2003
DSC-4678/2
FEATURES
••••• Memory storage capacity:
IDT72V3683
16,384 x 36
IDT72V3693
32,768 x 36
IDT72V36103 –
65,536 x 36
••••• Clock frequencies up to 100 MHz (6.5 ns access time)
••••• Clocked FIFO buffering data from Port A to Port B
••••• IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
••••• Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
••••• Serial or parallel programming of partial flags
••••• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
••••• Big- or Little-Endian format for word and byte bus sizes
••••• Retransmit Capability
••••• Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
••••• Mailbox bypass registers for each FIFO
••••• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
••••• Easily expandable in width and depth
••••• Auto power down minimizes power dissipation
••••• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
••••• Pin compatible with the lower density parts, IDT72V3623/
72V3633/72V3643/72V3653/72V3663/72V3673
••••• Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
FUNCTIONAL BLOCK DIAGRAM
Mail 1
Register
Programmable Flag
Offset Registers
Status Flag
Logic
EF/OR
AE
36
FF/IR
AF
36
Timing
Mode
FWFT
A0-A35
FS2
FS0/SD
FS1/
SEN
B0-B35
Write
Pointer
Read
Pointer
Mail 2
Register
MBF2
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
Port-B
Control
Logic
16
4678 drw 01
RAM ARRAY
16,384 x 36
32,768 x 36
65,536 x 36
CLKA
CSA
W/
RA
ENA
MBA
Port-A
Control
Logic
FIFO1
Mail1,
Mail2,
Reset
Logic
RS1
MBF1
36
PRS
36
36
RS2
36
FIFO
Retransmit
Logic
RT
RTM


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