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GS881Z36BGT-333I Datasheet(PDF) 27 Page - GSI Technology |
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GS881Z36BGT-333I Datasheet(HTML) 27 Page - GSI Technology |
27 / 39 page GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D) Rev: 1.04 10/2004 27/39 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. JTAG TAP Block Diagram Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Instruction Register ID Code Register Boundary Scan Register 0 1 2 0 ·· · · 31 30 29 1 2 0 Bypass Register TDI TDO TMS TCK Test Access Port (TAP) Controller · · · · · ··· · · Control Signals · |
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