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GS881Z32BT-333IT Datasheet(PDF) 31 Page - GSI Technology |
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GS881Z32BT-333IT Datasheet(HTML) 31 Page - GSI Technology |
31 / 39 page GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D) Rev: 1.04 10/2004 31/39 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. JTAG TAP Instruction Set Summary Instruction Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 RFU 110 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 BYPASS 111 Places Bypass Register between TDI and TDO. 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted. JTAG Port AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDDQ/2 Output reference level VDDQ/2 DQ VDDQ/2 50 Ω 30pF* JTAG Port AC Test Load * Distributed Test Jig Capacitance |
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