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K7M163625A Datasheet(PDF) 3 Page - Samsung semiconductor |
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K7M163625A Datasheet(HTML) 3 Page - Samsung semiconductor |
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3 / 18 page  512Kx36 & 1Mx18 Flow-Through NtRAMTM - 3 - Rev 3.0 Nov. 2003 K7M161825A K7M163625A 512Kx36 & 1Mx18-Bit Flow Through NtRAMTM The K7M163625A and K7M161825A are 18,874,368-bits Syn- chronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory uti- lizes all bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, Flow-Through SRAM allows output data to simply flow freely from the memory array. The K7M163625A and K7M161825A are implemented with SAMSUNG ′s high performance CMOS technology and is avail- able in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce. GENERAL DESCRIPTION FEATURES LOGIC BLOCK DIAGRAM • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • Three Chip Enable for simple depth expansion with no data contention . • A interleaved burst or a linear burst mode. • Asynchronous output enable control. • Power Down mode. • TTL-Level Three-State Outputs. • 100-TQFP-1420A • Operating in commeical and industrial temperature range. NtRAM TM and No Turnaround Random Access Memory are trademarks of Samsung. WE BWx CLK CKE CS1 CS2 CS2 ADV OE ZZ DQa0 ~ DQd7 or DQa0 ~ DQb8 ADDRESS ADDRESS REGISTER A ′0~A′1 36 or 18 DQPa ~ DQPd BUFFER DATA-IN REGISTER K REGISTER BURST ADDRESS COUNTER WRITE CONTROL LOGIC K A [0:18]or A [0:19] LBO A2~A18 or A2~A19 A0~A1 (x=a,b,c,d or a,b) 512Kx36, 1Mx18 MEMORY ARRAY FAST ACCESS TIMES Parameter Sym. -65 -75 Unit Cycle Time tCYC 7.5 8.5 ns Clock Access Time tCD 6.5 7.5 ns Output Enable Access Time tOE 3.5 3.5 ns |
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