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K7A801800A-14 Datasheet(PDF) 2 Page - Samsung semiconductor |
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K7A801800A-14 Datasheet(HTML) 2 Page - Samsung semiconductor |
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2 / 20 page  K7A801800A 256Kx36 & 512Kx18 Synchronous SRAM - 2 - Rev 1.0 July 2000 K7A803600A 256Kx36 & 512Kx18-bit Synchronous Pipelined Burst SRAM The K7A803600A and K7A801800A are 9,437,184-bit Syn- chronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 256K(512K) words of 36(18) bits and inte- grates address and control registers, a 2-bit burst address counter and added some new functions for high perfor- mance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated inter- nally in the system ′s burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC operated and determines burst sequence(lin- ear or interleaved). ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7A803600A and K7A801800A are fabricated using SAMSUNG ′s high performance CMOS technology and is available in a 100pin TQFP and 119BGA package. Multiple power and ground pins are utilized to minimize ground bounce. GENERAL DESCRIPTION FEATURES LOGIC BLOCK DIAGRAM • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O • 5V Tolerant Inputs Except I/O Pins. • Byte Writable Function. • Global Write Enable Controls a full bus-width write. • Power Down State via ZZ Signal. • LBO Pin allows a choice of either a interleaved burst or a linear burst. • Three Chip Enables for simple depth expansion with No Data Contention only for TQFP ; 2cycle Enable, 1cycle Disable. • Asynchronous Output Enable Control. • ADSP, ADSC, ADV Burst Control Pins. • TTL-Level Three-State Output. • 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package) CLK LBO ADV ADSC ADSP CS1 CS2 CS2 GW BW WEx OE ZZ DQa0 ~ DQd7 or DQa0 ~ DQb7 BURST CONTROL LOGIC BURST 256Kx36 , 512Kx18 ADDRESS CONTROL OUTPUT DATA-IN ADDRESS COUNTER MEMORY ARRAY REGISTER REGISTER BUFFER LOGIC A ′0~A′1 A0~A1 or A2~A18 or A0~A18 REGISTER FAST ACCESS TIMES PARAMETER Symbol -16 -15 -14 -10 Unit Cycle Time tCYC 6.0 6.7 7.2 10 ns Clock Access Time tCD 3.5 3.8 3.8 4.5 ns Output Enable Access Time tOE 3.5 3.8 3.8 4.5 ns DQPa ~ DQPd A0~A17 A2~A17 (x=a,b,c,d or a,b) DQPa,DQPb |
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