CY28381
Document #: 38-07546 Rev. **
Page 2 of 19
Pin Description[2]
Pin
Name
PWR
I/O
Description
6XIN
I
Oscillator Buffer Input. Connect to a crystal or to an external clock.
7
XOUT
VDDR
O
Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.
40,44
CPU[0:1]
VDDC
O
“True” Host Output Clocks. See Table 1 for frequencies and functionality.
39,43
CPUC[0:1]
VDDC
O
“Complementary” Host Output Clocks. See Table 1 for frequencies and
functionality.
16,17,20,23 PCI [0:5]
VDDP
O
PCI Clock Outputs. See Table 1.
14
FS3/PCIF0
VDDP
I/O
PD
Power-on Bidirectional Input/Output. At power-up, FS3 is the input. When
VTT_PWRGD transitions to a logic high, FS3 state is latched and this pin
becomes PCIF0 Clock Output. See Table 1.
15
FS4/PCIF1
VDDP
I/O
PD
Power-on Bidirectional Input/Output. At power-up, FS4 is the input. When
VTT_PWRGD transitions to a logic high, FS4 state is latched and this pin
becomes PCIF1 Clock Output. See Table 1.
2
FS0/REF0
VDDR
I/O
PD
Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When
VTT_PWRGD transitions to a logic high, FS0 state is latched and this pin
becomes REF0, buffered Output copy of the device’s XIN clock.
3
FS1/REF1
VDDR
I/O
PD
Power-on Bidirectional Input/Output. At power-up, FS1 is the input. When
VTT_PWRGD is transited to logic low, FS1 state is latched and this pin
becomes REF1, buffered Output copy of the device’s XIN clock.
4
FS2/REF2
VDDR
I/O
PD
Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When
VTT_PWRGD is transited to logic low, FS2 state is latched and this pin
becomes REF2, buffered Output copy of the device’s XIN clock.
38
IREF
I
Current Reference Programming Input for CPU Buffers. A resistor is
connected between this pin and VSS. See Figure 9.
33
PD#/
VTT_PRGD
VDDAGP
I
PU
Power-down Input/VTT Power Good Input. At power-up, VTT_PWRGD is
the input. When this input is transitions initially from low to high, the FS (0:4)
and MULT0 are latched. After the first low to high transition, this pin become
a PD# input with an internal pull-up. When PD# is asserted low, the device
enters power down mode. See power management function.
27
48M
VDD48M
O
Fixed 48MHz USB Clock Output.
26
24_48M/
MULT0
VDD48M
I/O
PU
Power-on Bidirectional Input/Output. At power-up, MULT0 is the input.
When VTT_PWRGD is transited to logic low, MULT0 state is latched and this
pin becomes 24_48M, SIO programmable clock output.
9,10
ZCLK (0:1)
VDDZ
O
HyperZip Clock Outputs. See Table 1.
34
SDATA
VDDAGP
I/O
Serial Data Input. Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open drain
output when acknowledging or transmitting data.
35
SCLK
VDDAGP
I
Serial Clock Input. Conforms to the SMBus specification.
12
SRESET#
VDDZ
O
PCI Clock Disable Input. If Byte12 Bit7 = 0, this pin becomes an SRESET#
open drain output, and the internal pulled up is not active. See system reset
description.
PCI_STP#
VDDZ
I
PU
System Reset Control Output. If Byte12 Bit7 = 1 (Default), this pin becomes
PCI Clock Disable Input. When PCI_STP# is asserted low, PCI (0:5) clocks
are synchronously disabled in a low state. This pin does not affect PCIF (0:1)
if they are programmed to be free-running clocks via the device’s SMBus
interface.
45
CPU_STP#
VDDSD
I
PU
CPU Clock Disable Input. When asserted low, CPU (0:1)T clocks are
synchronously disabled in a high state and CPU (0:1)C clocks are synchro-
nously disabled in a low state.
47
SDCLK
VDDSD
O
SDRAM Clock Output.
30,31
AGP (0:1)
VDDAGP
O
AGP Clock Outputs. See Table 1 for frequencies and functionality.
Note:
2.
PU = internal pull-up. PD = internal pull-down. T = Tri-level logic input with valid logic voltages of LOW =<0.8V, T =1.0 -1.8V and HIGH => 2.0V.