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S24VP04SI-BTE7 Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part # S24VP04SI-BTE7
Description  4K Serial E2PROM with a Precision Low-VCC Lockout Circuit
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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S24VP04SI-BTE7 Datasheet(HTML) 5 Page - List of Unclassifed Manufacturers

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S24VP04
5
2008 1.4 5/15/98
FIGURE 6. PAGE/BYTE WRITE MODE
WRITE OPERATIONS
The S24VP04 allows two types of write operations: byte
write and page write. The byte write operation writes a
single byte during the nonvolatile write period (tWR). The
page write operation allows up to 16 bytes in the same
page to be written during tWR.
Byte WRITE
After the slave address is sent (to identify the slave
device, specify high order word address and a read or
write operation), a second byte is transmitted which
contains the low 8 bit addresses of any one of the 512
words in the array.
Upon receipt of the word address, the S24VP04 responds
with an ACKnowledge. After receiving the next byte of
data, it again responds with an ACKnowledge. The mas-
ter then terminates the transfer by generating a STOP
condition, at which time the S24VP04 begins the internal
write cycle.
While the internal write cycle is in progress, the S24VP04
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 6 for the
address, ACKnowledge and data transfer sequence.
Page WRITE
The S24VP04 is capable of a 16-byte page write opera-
tion. It is initiated in the same manner as the byte-write
operation, but instead of terminating the write cycle after
the first data word, the master can transmit up to 15 more
words of data. After the receipt of each word, the
S24VP04 will respond with an ACKnowledge.
The S24VP04 automatically increments the address for
subsequent data words. After the receipt of each word,
the four low order address bits are internally incremented
by one. The high order five bits of the address byte remain
constant. Should the master transmit more than sixteen
words, prior to generating the STOP condition, the ad-
dress counter will “roll over,” and the previously written
data will be overwritten. As with the byte-write operation,
all inputs are disabled during the internal write cycle.
Refer to Figure 6 for the address, ACKnowledge and data
transfer sequence.
The next two bits are don’t care. The S24VP04 will
respond to all commands for device 1010.
Bank Select Bit
The next bit of the serial stream is the bank select bit. It is
used by the host to toggle between the two 2K-bit banks
of memory. It is, in effect, the most significant bit of the
word address, or A8.
Read/Write Bit
The last bit of the data stream defines the operation to be
performed. When set to “1,” a read operation is selected;
when set to “0,” a write operation is selected.
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
5
D
6
D
4
D
0
D
3
D
2
D
1
S
T
A
R
T
Word Address
Data Byte n
Data Byte n+15
S
T
O
P
A
C
K
Acknowledges Transmitted from
24VP04 to Master Receiver
Slave Address
Device
Type
Address
Read/Write
0= Write
A2,A1,BS
SDA
Bus
Activity
A
C
K
A
C
K
Master Sends Read
Request to Slave
Master Writes Word
Address to Slave
1 0 1 0
0
Data Byte n+1
A
C
K
Master Writes
Data to Slave
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Shading Denotes
24VP04
SDA Output Active
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Master Writes
Data to Slave
Master Writes
Data to Slave
Acknowledges Transmitted from
24043 to Master Receiver
If single byte-write only,
Stop bit issued here.
A
2
A
1
R
W
A
C
K
B
S
2008 ILL8 1.0


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