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UPD703111AF1-15-GA3-A Datasheet(PDF) 11 Page - NEC |
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UPD703111AF1-15-GA3-A Datasheet(HTML) 11 Page - NEC |
11 / 974 page User’s Manual U16031EJ4V1UD 11 5.1.1 Features..................................................................................................................................... 186 5.1.2 SRAM connection ...................................................................................................................... 187 5.1.3 SRAM, external ROM, external I/O access ................................................................................ 189 5.2 Page ROM Controller (ROMC) ...............................................................................................199 5.2.1 Features..................................................................................................................................... 199 5.2.2 Page ROM connection ............................................................................................................... 200 5.2.3 On-page/off-page judgment ....................................................................................................... 201 5.2.4 Page ROM configuration register (PRC) .................................................................................... 202 5.2.5 Page ROM access ..................................................................................................................... 203 5.3 SDRAM Controller (SDRAMC) ...............................................................................................209 5.3.1 Features..................................................................................................................................... 209 5.3.2 SDRAM connection.................................................................................................................... 209 5.3.3 Address multiplex function ......................................................................................................... 210 5.3.4 SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6) ................................... 216 5.3.5 SDRAM access.......................................................................................................................... 219 5.3.6 Refresh control function ............................................................................................................. 243 5.3.7 Self-refresh control function ....................................................................................................... 248 5.3.8 SDRAM initialization sequence .................................................................................................. 250 5.4 Cautions...................................................................................................................................253 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) ..................................................................254 6.1 Features ...................................................................................................................................254 6.2 Configuration...........................................................................................................................255 6.3 Control Registers ....................................................................................................................256 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) .............................................................. 256 6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) ....................................................... 258 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) ................................................................ 260 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3).................................................... 261 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) ........................................................ 264 6.3.6 DMA terminal count output control register (DTOC) .................................................................. 267 6.3.7 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) .............................................................. 268 6.3.8 DMA interface control register (DIFC) ........................................................................................ 274 6.4 Transfer Modes .......................................................................................................................275 6.4.1 Single transfer mode .................................................................................................................. 275 6.4.2 Single-step transfer mode .......................................................................................................... 277 6.4.3 Block transfer mode ................................................................................................................... 278 6.5 Transfer Types ........................................................................................................................279 6.5.1 2-cycle transfer .......................................................................................................................... 279 6.5.2 Flyby transfer ............................................................................................................................. 290 6.6 Transfer Target........................................................................................................................302 6.6.1 Transfer type and transfer target................................................................................................ 302 6.6.2 External bus cycles during DMA transfer ................................................................................... 304 6.7 DMA Channel Priorities ..........................................................................................................304 6.8 Next Address Setting Function .............................................................................................305 6.9 DMA Transfer Start Factors ...................................................................................................307 6.10 Terminal Count Output upon DMA Transfer End ................................................................309 6.11 Forcible Interruption...............................................................................................................310 |
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