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UPD780034Y Datasheet(PDF) 4 Page - NEC |
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UPD780034Y Datasheet(HTML) 4 Page - NEC |
4 / 42 page 4 µPD780016Y, 780018Y Internal ROM 48K bytes 60K bytes memory Internal high-speed RAM 1024 bytes Buffer RAM 32 butes Internal expansion RAM 1024 bytes Memory space 64K bytes General registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Instruction cycle On-chip instruction execution time selective function When main system clock selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at 5.0 MHz) When subsystem clock selected 122 µs (at 32.768 kHz) Instruction set • 16-bit operation • Multiplcation/division (8 bits × 8 bits,16 bits ÷ 8 bits) • Bit manipulation (set, reset, test, boolean operation) • BCD adjustment, etc. I/O ports Total : 88 • CMOS input : 9 • CMOS I/O : 79 A/D converter • 8-bit resolution × 8 channels Serial interface • 3-wire serial I/O mode (with automatic data transmit/receive function): 1 channel • 3-wire serial I/O mode (with time division transfer function) : 1 channel •I2C bus mode (supporting multi-task) : 1 channel Timer • 16-bit timer/event counter : 1 channel • 8-bit timer/event counter : 4 channels • Watch timer : 1 channel • Watchdog timer : 1 channel Timer output 5 (14-bit PWM output × 1, 8-bit PWM output × 2) Clock output 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (at main system clock of 5.0 MHz) 32.768 kHz (at subsystem clock of 32.768 kHz) Buzzer output 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock: at 5.0 MHz) Vectored Maskable Internal : 12 interrupt External : 7 sources Non-maskable Internal : 1 Software 1 Test input Internal : 1 External : 1 Supply voltage VDD = 2.7 to 5.5 V Package • 100-pin plastic QFP (14 × 20 mm) OVERVIEW OF FUNCTION Part Number Item µPD780016Y µPD780018Y |
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