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TMS470R1B768PGEQ Datasheet(PDF) 10 Page - Texas Instruments |
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TMS470R1B768PGEQ Datasheet(HTML) 10 Page - Texas Instruments |
10 / 46 page www.ti.com TMS470R1B768 16/32-Bit RISC Flash Microcontroller SPNS108 – AUGUST 2005 Table 2. Terminal Functions (continued) TERMINAL INTERNAL TYPE(1)(2) PULLUP/ DESCRIPTION NAME NO. PULLDOWN(3) SERIAL PERIPHERAL INTERFACE 5 (SPI5) SPI5CLK 60 SPI5 clock. SPI5CLK can be programmed as a GIO pin. SPI5ENA 61 SPI5 chip enable. SPI5ENA can be programmed as a GIO pin. SPI5SCS 46 3.3-V I/O IPD (20 µA) SPI5 slave chip select. SPI5SCS can be programmed as a GIO pin. SPI5SIMO 58 SPI5 data stream. Slave in/master out. Can be programmed as a GIO pin. SPI5SOMI 59 SPI5 data stream. Slave out/master in. Can be programmed as a GIO pin. ZERO-PIN PHASE-LOCKED LOOP (ZPLL) OSCIN 13 1.8-V I Crystal connection pin or external clock input OSCOUT 12 1.8-V O External crystal connection pin Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator PLLDIS 73 3.3-V I IPD (20 µA) becomes the system clock. If not in bypass mode, TI recommends that this pin be connected to ground or pulled down to ground by an external resistor. SERIAL COMMUNICATIONS INTERFACE 1 (SCI1) SCI1CLK 89 3.3-V I/O IPD (20 µA) SCI1 clock. SCI1CLK can be programmed as a GIO pin. SCI1RX 91 3.3-V I/O IPU (20 µA) SCI1 data receive. SCI1RX can be programmed as a GIO pin. SCI1TX 90 3.3-V I/O IPU (20 µA) SCI1 data transmit. SCI1TX can be programmed as a GIO pin. SERIAL COMMUNICATIONS INTERFACE 2 (SCI2) SCI2CLK 45 3.3-V I/O IPD (20 µA) SCI2 clock. SCI2CLK can be programmed as a GIO pin. SCI2RX 43 3.3-V I/O IPU (20 µA) SCI2 data receive. SCI2RX can be programmed as a GIO pin. SCI2TX 44 3.3-V I/O IPU (20 µA) SCI2 data transmit. SCI2TX can be programmed as a GIO pin. SYSTEM MODULE (SYS) Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output of CLKOUT 83 3.3-V I/O IPD (20 µA) SYSCLK, ICLK, or MCLK. Input master chip power-up reset. External VCC monitor circuitry must assert a PORRST 32 3.3-V I IPD (20 µA) power-on reset. Bidirectional reset. The internal circuitry can assert a reset, and an external system reset can assert a device reset. RST 15 3.3-V I/O IPU (20 µA) On this pin, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor be connected to this pin. WATCHDOG/REAL-TIME INTERRUPT (WD/RTI) Analog watchdog reset. The AWD pin provides a system reset if the WD KEY is not written in time by the system, providing an external RC network circuit is connected. If the user is not using AWD, TI recommends that this pin be connected to ground or pulled down to ground by an external resistor. AWD 72 3.3-V I/O IPD (20 µA) For more details on the external RC network circuit, see the TMS470R1x System Module Reference Guide (literature number SPNU189) and the application note Analog Watchdog Resistor, Capacitor and Discharge Interval Selection Constraints (literature number SPNA005). TEST/DEBUG (T/D) TCK 76 3.3-V I IPD (20 µA) Test clock. TCK controls the test hardware (JTAG). Test data in. TDI inputs serial data to the test instruction register, test data TDI 74 3.3-V I IPU (20 µA) register, and programmable test address (JTAG). Test data out. TDO outputs serial data from the test instruction register, test TDO 75 3.3-V O IPD (20 µA) data register, identification register, and programmable test address (JTAG). 10 |
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