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HYMP512R724-C4 Datasheet(PDF) 4 Page - Hynix Semiconductor |
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HYMP512R724-C4 Datasheet(HTML) 4 Page - Hynix Semiconductor |
4 / 18 page HYMP512R72(L)4 Rev. 0.2 / July 2004 4 PIN DESCRIPTION PIN Location Pin Pin Description Pin Pin Description CK0 Clock Input,positive line ODT[1:0] On Die Termination Inputs CK0 Clock input,negative line VDDQ DQs Power Supply CKE0~CKE1 Clock Enable Input DQ0~DQ63 Data Input/Output RAS Row Address Strobe CB0~CB7 Data check bits Input/Output CAS Column Address Strobe DQS(0~8) Data strobes WE Write Enable DQS(0~8) Data strobes,negative line S0 Chip Select Input DM(0~8),DQS(9~17) Data Maskes/Data strobes A0~A9,A11~A13 Address input DQS(9~17) Data strobes,negative line A10/AP Address input/Autoprecharge RFU Reserved for Future Use BA0, BA1 SDRAM Bank Address NC No Connect SCL Serial Presence Detect(SPD) Clock Input TEST Memory bus test tool(Not Connected and Not Usable on DIMMs) SDA SPD Data Input/Output VDD Core Power SA0~SA2 E2PROM Address Inputs VDDQ I/O Power Supply Par_In Parity bit for the Address and Control bus VSS Ground Err_Out Parity error found on the Addre VREF Reference Power Supply RESET Reset Enable VDDSPD Power Supply for SPD CB0~CB7 Data Strobe Inputs/Outputs 1 pin Front Side 64 pin 65 pin 120 pin 121 pin Back Side 184 pin 185 pin 240 pin |
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