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HYMP512R724-E3 Datasheet(PDF) 3 Page - Hynix Semiconductor

Part # HYMP512R724-E3
Description  240pin Registered DDR2 SDRAM DIMMs based on 512 Mb 1st ver.
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HYMP512R724-E3 Datasheet(HTML) 3 Page - Hynix Semiconductor

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Rev. 1.0 / Apr. 2005
3
1
240pin Registered DDR2 SDRAM DIMMs
Input/Output Functional Description
Symbol
Type
Polarity
Pin Description
CK0
IN
Positive
Edge
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CK0IN
Negative
Edge
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CKE[1:0]
IN
Active
High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
S[1:0]
IN
Active
Low
Enables the associated DDR2 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
ODT[1:0]
IN
Active
High
On-Die Termination signals.
RAS, CAS, WE
IN
Active
Low
When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define
the command being entered.
Vref
Supply
Reference voltage for SSTL18 inputs
VDDQ
Supply
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all
current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
BA[1:0]
IN
-
Selects which DDR2 SDRAM internal bank of four is activated.
A[9:0],
A10/AP
A[13:11]
IN
-
During a Bank Activate command cycle, Address input difines the row address(RA0~RA13)
During a Read or Write command cycle, Address input defines the column address when sam-
pled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged.
If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in con-
junction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-
charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define
which bank to precharge.
DQ[63:0],
CB[7:0]
IN
-
Data and Check Bit Input/Output pins.
DM[8:0]
IN
Active
High
DM is an input mask signal for write data. Input data is masked when DM is sampled High coin-
cident with that input data during a write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
VDD,VSS
Supply
Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are
tied to VDD/VDDQ planes on these modules.
DQS[17:0]
I/O
Positive
Edge
Positive line of the differential data strobe for input and output data
DQS[17:0]
I/O
Negative
Edge
Negative line of the differential data strobe for input and output data
SA[2:0]
IN
-
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD
EEPROM address range.
SDA
I/O
-
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may
be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up.
SCL
IN
-
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from SCL to VDDSPD to act as a pull up on the system board.
VDDSPD
Supply
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane.
EEPROM supply is operable from 1.7V to 3.6V.
RESET
IN
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When
low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will
be set to low level (the PLL will remain synchronized with the input clock)
Par_In
IN
Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)
Err_Out
OUT
Parity error found in the Address and Control bus
TEST
Used by memory bus analysis tools(unused on memory DIMMs)


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