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HYMP125R72M4-E3 Datasheet(PDF) 1 Page - Hynix Semiconductor |
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HYMP125R72M4-E3 Datasheet(HTML) 1 Page - Hynix Semiconductor |
1 / 24 page This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Apr. 2005 1 240pin Registered DDR2 SDRAM DIMMs based on 512 Mb 1st ver. This Hynix registered Dual In-Line Memory Module (DIMM) series consists of 512Mb 1st ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 512Mb 1st ver. based Registered DDR2 DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES ORDERING INFORMATION Part Name Density Organization # of DRAMs # of ranks Materials HYMP564R728-E3/C4 512MB 64Mx72 9 1 Leaded HYMP512R728-E3/C4 1GB 128Mx72 18 2 Leaded HYMP512R724-E3/C4 1GB 128Mx72 18 1 Leaded HYMP125R72M4-E3/C4 2GB 256Mx72 36 2 Leaded HYMP564R72P8-E3/C4 512MB 64Mx72 9 1 Lead free HYMP512R72P8-E3/C4 1GB 128Mx72 18 2 Lead free HYMP512R72P4-E3/C4 1GB 128Mx72 18 1 Lead free HYMP125R72MP4-E3/C4 2GB 256Mx72 36 2 Lead free • JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply • All inputs and outputs are compatible with SSTL_1.8 interface •4 Bank architecture •Posted CAS • Programmable CAS Latency 3 , 4 , 5 • OCD (Off-Chip Driver Impedance Adjustment) • ODT (On-Die Termination) • Fully differential clock operations (CK & CK) • Programmable Burst Length 4 / 8 with both sequen- tial and interleave mode • Auto refresh and self refresh supported • 8192 refresh cycles / 64ms • Serial presence detect with EEPROM • DDR2 SDRAM Package: 60ball FBGA • 133.35 x 30.00 mm form factor • Lead-free Products are RoHS compliant |
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